TLK3134_1 Datasheet, PDF (107/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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SIGNAL
RXD_[31:0]
LOCATION
H2
H1
H5
G3
G4
F1
F5
E2
E1
E3
D2
E5
B1
D4
B2
E6
A3
B3
C5
B4
A4
B6
A6
A8
B8
D8
B9
A10
C9
A11
D10
E10
H4
F4
D3
RXC_[7:0]
D5
E7
B7
E8
C10
TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
Table 3-4. Parallel Data Pins (continued)
VOLTAGE
TYPE
DESCRIPTION
VDDQ
1.5/1.8 V
HSTL
Output
Receive Data Pins (XGMII) Parallel interface data pins.
See the following tables for functionality per application mode:
Table 2-3 XAUI - Lane To Functional Pin Mapping (XAUI_ORDER = 1)
Table 2-4 10GFC - Lane To Functional Pin Mapping (XAUI_ORDER = 0)
Table 2-5 RGMII - Lane To Functional Pin Mapping
Table 2-6 RTBI - Lane To Functional Pin Mapping
Table 2-7 TBI - Lane To Functional Pin Mapping
Table 2-8 GMII - Lane To Functional Pin Mapping
Table 2-9 EBI - Lane To Functional Pin Mapping
Table 2-10 REBI - Lane To Functional Pin Mapping
Table 2-11 NBI - Lane To Functional Pin Mapping
Table 2-12 RNBI - Lane To Functional Pin Mapping
Table 2-13 TBID - Lane To Functional Pin Mapping
Table 2-15 NBID - Lane To Functional Pin Mapping
VDDQ
1.5/1.8 V
HSTL
Output
Receive Data Control (XGMII) XGMII Control inputs.
See the following tables for functionality per application mode:
Table 2-3 XAUI - Lane To Functional Pin Mapping (XAUI_ORDER = 1)
Table 2-4 10GFC - Lane To Functional Pin Mapping (XAUI_ORDER = 0)
Table 2-5 RGMII - Lane To Functional Pin Mapping
Table 2-6 RTBI - Lane To Functional Pin Mapping
Table 2-7 TBI - Lane To Functional Pin Mapping
Table 2-8 GMII - Lane To Functional Pin Mapping
Table 2-9 EBI - Lane To Functional Pin Mapping
Table 2-10 REBI - Lane To Functional Pin Mapping
Table 2-11 NBI - Lane To Functional Pin Mapping
Table 2-12 RNBI - Lane To Functional Pin Mapping
Table 2-13 TBID - Lane To Functional Pin Mapping
Table 2-15 NBID - Lane To Functional Pin Mapping
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Device Reset Requirements/Procedure 107