TLK3134_1 Datasheet, PDF (42/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
FAIL3
When in this state, the Column Alignment Sync bit is '1' in MDIO registers 4/5.24.12. During
this state the alignment character code detect circuit is active on each channel but the
column re-alignment is disabled. If complete alignment column is not detected in the correct
position within the Inter-Packet Gap, the column state machine will transition to state
UNALIGN. If a complete alignment column is detected in the correct position within the
Inter-Packet Gap, the column state machine will transition to state FAIL2.
RDP/N0
Any Valid
Code
K28.3
K28.5
K28.0
RR XX XXX X X X X X AA AA AAA AAA K KK K K KKKKKR RR R RR RR RRK
RDP/N1
RR XX XX X X X X X X AA AA AAA AAA K KK K K KKKKKR RR R RR RR
RDP/N2 ^{R R X X X X X X X X X X A A A A A A A A A A K K K K K K K K K K R R R R R R R R R R K K K K}
RDP/N3
R R XX X X X X X X X X AA AA A AA A AA K KK K K KK KK K R RR R RR RR R R
RCLK
RXD(7:0)
RXD(15:8)
RXD(23:16)
RXD(31:24)
undefined
undefined
A
K
undefined
undefined
A
K
undefined
undefined
A
K
undefined
undefined
A
K
Figure 2-25. Channel Deskew Using Alignment Code
2.7.25 Inter-Packet Gap Management
When in XAUI mode, the TLK3134 replaces the idle codes (see Table 2-15) during the Inter-Packet Gap
(IPG) with the necessary codes to perform all channel alignment, byte alignment, and clock tolerance
compensation as defined in IEEE 802.3ae 10Gbps Ethernet Standard. According to the Ethernet
Standard, a valid packet must begin on TXD(7:0) of the XGMII. However, due to variable packet sizes, the
IPG can begin on any channel. The TLK3134 will replace idle codes latched on the same XGMII clock
edge as the end of packet code with /K/ codes (as shown in Figure 2-26).
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Detailed Description
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