TLK3134_1 Datasheet, PDF (43/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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Packet
TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
IPG
TXD(7:0) I I S D D D D ... D D D D I I I I I I
Input
TXD(15:8)
TXD(23:16)
I I D D D D D ... D D D T I I I I I I
I I D D D D D ... D D D I I I I I I I
TXD(31:24) I I D D D D D ... D D D I I I I I I I
TDP/N0 ^{K R S D D D D ... D D D D A R R K K R}
Output
TDP/N1 ^{K R D D D D D ... D D D T A R R K K R}
TDP/N2 K R D D D D D ... D D D K A R R K K R
TDP/N3 K R D D D D D ... D D D K A R R K K R
S = Start of Packet, D = Data, T = End of Packet,
A = K28.3, K = K28.5, R = K28.0, I = Idle
Figure 2-26. Inter-Packet Gap Management
The subsequent idles in the IPG will be replaced by “columns” of channel alignment codes (K28.3), byte
alignment codes (K28.5), or clock tolerance compensation codes (K28.0). The state machine which
governs the IPG replacement procedure is illustrated in Figure 2-27, with notation defined in Table 2-18.
Note that any IPG management state will transition to send data if the IPG is terminated.
The repetition of the “/A/” pattern on each serial channel allows the FIFOs to remove or add the required
phase and frequency difference to align the data from all four serial links of a XAUI channel and allow
output of the aligned 32 bit wide data on a single edge of the receive clock, RCLK, as shown in
Figure 2-25.
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Detailed Description
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