English
Language : 

TLK3134_1 Datasheet, PDF (86/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver
TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
BIT(s)
4/5.37889.15
4/5.37889.14
4/5.37889.13:8
ADDRESS: 0x9401
NAME
Lock_en
Write_en
Delay_sel[5:0]
4/5.37889.7:5 Offset[2:0]
4/5.37889.3 Filter_en
Table 2-147. TX1_DLL_CONTROL
DEFAULT: 0x0008
DESCRIPTION
For TI use only
For TI use only
DLL delay control. For TI use only
Phase shift control. Adds or removes delay element. Each delay element
is 0.15ns. Refer Table 2-154: DLL Offset Control
When asserted, the internal filter is used to reduce the cycle to cycle jitter
of the output clock.
www.ti.com
ACCESS
RW
BIT(s)
4/5.37890.15
4/5.37890.14
4/5.37890.13:8
ADDRESS: 0x9402
NAME
Lock_en
Write_en
Delay_sel[5:0]
4/5.37890.7:5 Offset[2:0]
4/5.37890.3 Filter_en
Table 2-148. TX2_DLL_CONTROL
DEFAULT: 0x0008
DESCRIPTION
For TI use only
For TI use only
DLL delay control. For TI use only
Phase shift control. Adds or removes delay element. Each delay element
is 0.15ns. Refer Table 2-154: DLL Offset Control
When asserted, the internal filter is used to reduce the cycle to cycle jitter
of the output clock.
ACCESS
RW
BIT(s)
4/5.37891.15
4/5.37891.14
4/5.37891.13:8
ADDRESS: 0x9403
NAME
Lock_en
Write_en
Delay_sel[5:0]
4/5.37891.7:5 Offset[2:0]
4/5.37891.3 Filter_en
Table 2-149. TX3_DLL_CONTROL
DEFAULT: 0x0008
DESCRIPTION
For TI use only
For TI use only
DLL delay control. For TI use only
Phase shift control. Adds or removes delay element. Each delay element
is 0.15 ns. Refer Table 2-154: DLL Offset Control
When asserted, the internal filter is used to reduce the cycle to cycle jitter
of the output clock.
ACCESS
RW
BIT(s)
4/5.37892.15
4/5.37892.14
4/5.37892.13:8
ADDRESS: 0x9404
NAME
Lock_en
Write_en
Delay_sel[5:0]
4/5.37892.7:5 Offset[2:0]
4/5.37892.3 Filter_en
Table 2-150. RX0_DLL_CONTROL
DEFAULT: 0x0008
DESCRIPTION
For TI use only
For TI use only
DLL delay control. For TI use only
Phase shift control. Adds or removes delay element. Each delay element
is 0.15 ns. Refer Table 2-154: DLL Offset Control
When asserted, the internal filter is used to reduce the cycle to cycle jitter
of the output clock.
ACCESS
RW
86
Detailed Description
Submit Documentation Feedback