TLK3134_1 Datasheet, PDF (33/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
2.7.12 Parallel Interface Clocking Modes
The TLK3134 supports source centered timing and source aligned DDR timing on the parallel receive
output bus. TLK3134 also supports rising edge aligned and falling edge aligned SDR timing on the parallel
receive output bus. See Figure 2-18 for more details.
RXCLK
Source Centered (DDR)
RXD
RXC
t_SETUP
t_HOLD
Data
t_SETUP
t_HOLD
Data
Source Aligned (DDR)
RXD
RXC
Data
Falling Edge Aligned (SDR)
RXD
RXC
Data
Data
Data
Data
Rising Edge Aligned (SDR)
RXD
RXC
Data
Data
Figure 2-18. Receive Interface Timing – Source Centered/Aligned
The transmit input timing modes are shown in Figure 2-19.
In the receive data path a FIFO, placed on the output of the serial to parallel conversion logic for each
serial link, compensates for channel skew, clock phase and frequency tolerance differences between the
recovered clocks for each serial links and the receive output clock, RCLK.
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