TLK3134_1 Datasheet, PDF (5/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
2-37 CL22 - Management Interface Write Timing................................................................................... 50
2-38 CL22 – Indirect Address Method – Address Write............................................................................ 50
2-39 CL22 – Indirect Address Method – Data Write................................................................................ 51
2-40 CL22 – Indirect Address Method – Address Write............................................................................ 51
2-41 CL22 – Indirect Address Method – Data Read................................................................................ 51
3-1 Device Pinout Diagram – Part 1 (Top View) ................................................................................. 110
3-2 Device Pinout Diagram – Part 2 (Top View) ................................................................................. 111
4-1 Transmit Output Waveform Parameter Definitions.......................................................................... 116
4-2 Transmit Template............................................................................................................... 116
4-3 Receive Template ............................................................................................................... 117
4-4 Input Jitter ........................................................................................................................ 117
4-5 HSTL (DDR Timing Mode Only) Source Centered Output Timing Requirements ...................................... 120
4-6 HSTL (DDR Timing Mode Only) Source Aligned Output Timing Requirements ........................................ 120
4-7 HSTL (SDR Timing Mode Only) Rising Edge Aligned Output Timing Requirements .................................. 121
4-8 HSTL (SDR Timing Mode Only) Falling Edge Aligned Output Timing Requirements .................................. 121
4-9 HSTL (DDR Timing Mode Only) Source Centered Data Input Timing Requirements .................................. 122
4-10 HSTL (DDR Timing Mode Only) Source Aligned Data Input Timing Requirements .................................... 122
4-11 HSTL (SDR Timing Mode Only) Falling Edge Aligned (Rising Edge Sampled) Data Input Timing Requirements . 123
4-12 HSTL (SDR Timing Mode Only) Rising Edge Aligned (Falling Edge Sampled) Data Input Timing Requirements . 123
4-13 MDIO Read/Write Timing....................................................................................................... 124
4-14 HSTL I/O Schematic ............................................................................................................ 124
4-15 JTAG Timing ..................................................................................................................... 125
4-16 TLK3134 Application Mode vs Interface Timing Mode Support ........................................................... 126
4-17 PACKAGE Information (Package Designator = ZEL)....................................................................... 127
4-18 Worst Case Device Power Dissipation ....................................................................................... 128
A-1 Reference Clock Selection – XAUI – 10 GbE Mode ........................................................................ 129
A-2 Reference Clock Selection – 10 Gigabit Fibre Channel Mode ............................................................ 130
A-3 Reference Clock Selection – Gigabit Ethernet Mode ....................................................................... 130
A-4 Reference Clock Selection – 1X/2X Fibre Channel Mode ................................................................. 131
A-5 Reference Clock Selection – OBSAI Mode .................................................................................. 131
A-6 Reference Clock Selection – CPRI Mode .................................................................................... 132
A-7 Reference Clock Selection – 9/10 Bit SERDES Mode – Full Rate (SPEED[1:0] == 00)............................... 132
A-8 Reference Clock Selection – 9/10 Bit SERDES Mode – Half Rate (SPEED[1:0] == 01) .............................. 133
A-9 Reference Clock Selection –9/10 Bit SERDES Mode – Quarter Rate (SPEED[1:0] == 10)........................... 133
A-10 Reference Clock Selection – 8 Bit SERDES Mode – Full Rate (SPEED[1:0] == 00) .................................. 134
A-11 Reference Clock Selection – 8 Bit SERDES Mode – Half Rate (SPEED[1:0] == 01) .................................. 134
A-12 Reference Clock Selection – 8 Bit SERDES Mode – Quarter Rate (SPEED[1:0] == 10).............................. 135
A-13 Standard Based Jitter Cleaner/SERDES Provisioning ..................................................................... 136
A-14 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (2x) Provisioning ................................................... 137
A-15 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (1x) Provisioning ................................................... 138
A-16 9/10 BIT SERDES Mode – Jitter Cleaner/SERDES (0.5x) Provisioning ................................................. 139
List of Figures
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