TLK3134_1 Datasheet, PDF (75/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
VALUE
0000
0001
0010
0011
0100
0101
0110
0111
Table 2-104. Transmit De-emphasis Control
4/5.36874/36876/36878/36880 [7:4]
AMPLITUDE REDUCTION
%
dB
VALUE
0
0
1000
4.76
-0.42
1001
9.52
-0.87
1010
14.28
-1.34
1011
19.04
-1.83
1100
23.8
-2.36
1101
28.56
-2.92
1110
33.32
-3.52
1111
AMPLITUDE REDUCTION
%
dB
38.08
-4.16
42.85
-4.86
47.61
-5.61
52.38
-6.44
57.14
-7.35
61.9
-8.38
66.66
-9.54
71.42
-10.87
VALUE
000
001
010
011
Table 2-105. Output Swing Control
4/5.36874/36876/36878/36880 [11:9]
AMPLITUDE (mVdfpp)
VALUE
125
100
250
101
500
110
625
111
AMPLITUDE (mVdfpp)
750
1000
1250
1375
Table 2-106. SERDES_TEST_CONFIG_TX⁽¹⁾
BIT(s)
4/5.36881.10:8
4/5.36881.7:6
4/5.36881.5:4
4/5.36881.3
4/5.36881.2
4/5.36881.1:0
ADDRESS: 0x9011
DEFAULT: 0x0000
NAME
DESCRIPTION
Reserved
Reserved for TI test
LOOPBACK_TX
00 = Disabled
01 = Pad loopback. For TI purposes only
10 = Inner loopback (CML driver disabled)
11 = Inner loopback (CML driver enabled)
CLKBYPASS_TX
PLL Bypass control in test mode
00 = No bypass
01 = Reserved
10 = Functional bypass. Macros run using TESCLKT
11 = Refclk observe (Reserved. For TI purposes only)
ENRXPATT_TX
0 – Disables test pattern verification in SERDES TX macro.
1 – Enables test pattern verification in SERDES TX macro.
ENTXPATT_TX
0 – Disables test pattern generation in SERDES TX macro.
1 – Enables test pattern generation in SERDES TX macro.
TESTPATT_TX
Valid when ENTXPATT_TX, ENRXPATT_TX, ENTEST_TX are set
00 = Reserved (Default)
01 = Clock pattern (Half baud clock pattern with period of 2UI)
10 = 2⁷ - 1 PRBS pattern
11 = 2²³ – 1 PRBS pattern
(1) Above control bits are only for vendor testing only. Customer should leave them at their default values
ACCESS
RW
RW
RW
RW
RW
RW
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