TLK3134_1 Datasheet, PDF (62/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
BIT(s)
4/5.32807. 15
4/5.32807. 14
4/5.32807. 13
4/5.32807. 12
4/5.32807. 11
4/5.32807. 10
4/5.32807. 9
4/5.32807. 8
Table 2-70. CHANNEL_SYNC_CONTROL
ADDRESS: 0x8027
NAME
Lane 3 channel sync bypass
Lane 2 channel sync bypass
Lane 1 channel sync bypass
Lane 0 channel sync bypass
Lane 3 channel sync freeze
Lane 2 channel sync freeze
Lane 1 channel sync freeze
Lane 0 channel sync freeze
DEFAULT: 0x0000
DESCRIPTION
When set, channel synchronization for the corresponding lane is
bypassed. (Default 1’b0)
When set, freezes the last acquired word alignment for the
corresponding lane. (Default 1’b0)
BIT(s)
4/5.32808. 15
4/5.32808. 11
4/5.32808. 7
4/5.32808. 3
Table 2-71. XGMII_IO_MODE_CONTROL
ADDRESS: 0x8028
DEFAULT: 0x0080
NAME
DESCRIPTION
XAUI Tx Edge Align
When set selects data relationship with the clock on the transmit side
0 – Source centered (Default 1’b0)
1 – Source aligned
XAUI Rx Edge Align
When set selects data relationship with the clock on the receive side
0 – Source centered (Default 1’b0)
1 – Source aligned
RCLK Output Enable
0 – Disables RCLK output
1 – Enables RCLK output (Default 1’b1)
XAUI Isolate
Setting this bit high isolates the XGXS core from the XGMII interface.
Inputs are ignored; Outputs are set to high impedance.
1 = Isolate is enabled
0 = Normal operation (Default 1’b0)
BIT(s)
4/5.32809.15
Table 2-72. 10G_MODE_CONTROL
ADDRESS: 0x8029
DEFAULT: 0x0000
NAME
DESCRIPTION
XAUI order
When set selects XAUI/10GFC mode. Logically OR’ed with CODE pin.
0 = 10 GFC mode (Default 1’b0)
1 = XAUI mode
BIT(s)
4/5.32810. 15:14
Table 2-73. RX_CLK_OUTPUT_CONTROL
ADDRESS: 0x802A
DEFAULT: 0x0000
NAME
DESCRIPTION
RX_CLK output clock
select
These control bits select the clock to be sent out on receive parallel
output clock (RX_CLK)
00 = Selects SERDES TX clock
01 = Selects Jitter cleaned clock (Selecting the jitter cleaned clock while
the jitter cleaner PLL is disabled is not recommended)
10 = Selects SERDES RX clock
11 = Reserved
ACCESS
RW
RW
ACCESS
RW
RW
RW
RW
ACCESS
RW
ACCESS
RW
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Detailed Description
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