TLK3134_1 Datasheet, PDF (41/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
2.7.24 Column State Descriptions:
UNALIGN
This is the initial state for the column state machine upon device power up or reset. If any of
the channel state machines are set to UNSYNC, the column state is set to UNALIGN. In this
state, the column state machine will search for alignment character codes (K28.3 or /A/) on
each channel and align the FIFO pointers on each channel to the /A/ character code. While
in this state, the Column Alignment Sync bit is set to '0' in MDIO registers 4/5.24.12,
indicating the column is not aligned.⁽²⁾ The column state will transition to the DET1 state
upon the detection and alignment of /A/ character codes in all four channels.
DET1
During this state, the alignment character code detect circuit is active on each channel but
the column re-alignment is disabled. The column state machine will remain in this state
looking for a column of alignment character codes. If an incomplete alignment column is
detected (alignment character codes not found on all channels) or a deskew error is
detected, the column state machine will transition to state UNALIGN. While in this state, the
Column Alignment Sync bit is set to '0' in MDIO registers 4/5.24.12 indicating the column is
not aligned.⁽²⁾ Detection of a complete alignment column will cause the column state
machine to transition to state DET2.
DET2
During this state, the alignment character code detect circuit is active on each channel but
the column re-alignment is disabled. The column state machine will remain in this state
looking for a column of alignment character codes. If an incomplete alignment column is
detected (alignment character codes not found on all channels) or a deskew error is
detected, the column state machine will transition to state UNALIGN. While in this state, the
Column Alignment Sync bit is set to '0' in MDIO registers 4/5.24.12 indicating the column is
not aligned.⁽²⁾ Detection of a complete alignment column will cause the column state
machine to transition to state DET3.
DET3
During this state, the alignment character code detect circuit is active on each channel but
the column re-alignment is disabled. The column state machine will remain in this state
looking for a column of alignment character codes. If an incomplete alignment column is
detected (alignment character codes not found on all channels) or a deskew error is
detected, the column state machine will transition to state UNALIGN. While in this state, the
Column Alignment Sync bit is set to '0' in MDIO registers 4/5.24.12 indicating the column is
not aligned.⁽²⁾ Detection of a complete alignment column will cause the column state
machine to transition to state ALIGN.
ALIGN
This is the normal state for receiving data. When in this state, the column state machine will
set the Column Alignment Sync bit to '1' in MDIO registers 4/5.24.12 indicating all channels
are aligned. During this state the alignment character code detect circuit is active on each
channel but the column re-alignment is disabled. If a deskew error is detected in the correct
position within the Inter-Packet Gap, the column state machine will transition to state FAIL1.
FAIL1
When in this state, the Column Alignment Sync bit is '1' in MDIO registers 4/5.24.12. During
this state the alignment character code detect circuit is active on each channel but the
column re-alignment is disabled. If a complete alignment column is not detected in the
correct position within the Inter-Packet Gap, the column state machine will transition to state
FAIL2. If a complete alignment column is detected in the correct position within the
Inter-Packet Gap, the column state machine will transition to state ALIGN.
FAIL2
When in this state, the Column Alignment Sync bit is '1' in MDIO registers 4/5.24.12. During
this state the alignment character code detect circuit is active on each channel but the
column re-alignment is disabled. If a complete alignment column is not detected in the
correct position within the Inter-Packet Gap, the column state machine will transition to state
FAIL3. If a complete alignment column is detected in the correct position within the
Inter-Packet Gap, the column state machine will transition to state FAIL1.
(2) The XGXS Lane Alignment bit = '0' will cause a local fault to be output on the receive data bus.
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