TLK3134_1 Datasheet, PDF (15/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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Line Card
4
RCLK
RDP/N[3:0]
RD(31:0)
RC(3:0)
TLK3134
4
TDP/N[3:0]
TCLK
TD(31:0)
TC(3:0)
MAC/
PACKET
PROCESSOR
TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
FRAMER/
PCS
PHY/
OPTICS
4
RCLK
RDP/N[3:0]
RD(31:0)
RC(3:0)
TLK3134
4
TDP/N[3:0]
TCLK
TD(31:0)
TC(3:0)
SWITCH
FABRIC
Figure 1-2. System Block Diagram – XAUI Backplane
REFCLK_P
REFCLK_N
REFCLK
RXBCLK[0]
HSTL_2X_CLK
REF_SEL[1:0]
00
REFCLK
01
Divider
1X ^REF_DIV[6:0]
Jitter Cleaner
PLL Core
PLL
Feedback
Divider
FB_DIV[6:0]
00
RXBYTE_CLK 01
10
RXB_SEL[1:0] ¹¹
00
DELAY_CLK ₀₁
10
DEL_SEL[1:0] ¹¹
Second PLL
Output
Divider
RXB_DIV[6:0]
Third PLL
Output
Divider
DEL_DIV[6:0]
First PLL Output
Divider
RXTX_DIV[6:0]
TX_SEL[1:0]
00
01 REFCLK_TX
10
11
00
01 REFCLK_RX
10
11
SERDES TX
P2S
P2S
PLL
P2S
P2S
SERDES RX
S2P
S2P
PLL
S2P
S2P
TX3P/N
TX2P/N
TX1P/N
TX0P/N
RX3P/N
RX2P/N
RX1P/N
RX0P/N
RX_SEL[1:0]
(2.875 Ghz Min., 3 Ghz Typ., 3.125 Ghz Max.)
HSTL Output
00
Divider
01
HSTL_DIV2[6:0]
10
11
HSTL_SEL[1:0]
Fourth PLL
Output
Divider
HSTL_DIV1[6:0]
Note: Default Mux Selects Are Underlined.
Figure 1-3. Block Diagram – TLK3134 Clocking Architecture
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Introduction
15