TLK3134_1 Datasheet, PDF (37/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
2.7.18 Comma Detect and 8B/10B Decoding
When parallel data is clocked into a parallel to serial converter, the byte boundary that was associated
with the parallel data is lost in the serialization of the data. When the serial data is received and converted
to parallel format again, a method is needed to be able to recognize the byte boundary again. Generally
this is accomplished through the use of a synchronization pattern. This is a unique pattern of 1’s and 0’s
that either cannot occur as part of valid data or is a pattern that repeats at defined intervals. 8B/10B
encoding contains a character called the comma (b’0011111 or b’1100000) which is used by the comma
detect circuit to align the received serial data back to its original byte boundary. The channel
synchronization block detects the comma pattern found in the K28.5 character, generating a
synchronization signal aligning the data to their 10-bit boundaries for decoding. It then converts the data
back into 8-bit data. It is important to note that the comma can be either a (b’0011111) or the inverse
(b’1100000) depending on the running disparity. The TLK3134 decoder will detect both patterns.
The reception of K-characters is reported by the assertion of receive control pin, RXC(3:0) for the
corresponding byte on the XGMII receive bus. When a code word error or running disparity error is
detected in the decoded data received on a serial link, the receive control pin is asserted and an 0xFE is
placed on the receive data bus for that channel, as shown in Table 2-17.
Table 2-17. Receive Data Controls
EVENT
Normal Data
Normal K-character
Code word error or running disparity error
RECEIVE DATA BUS
RXD[x:x–7]
XX
Valid K-code
FE
RXC(3:0)
0
1
1
2.7.19 Channel Initialization and Synchronization
The TLK3134 has a synchronization state machine which is responsible for handling link initialization and
synchronization for each channel. The initialization and synchronization state diagram is provided in
Figure 2-22. The status of any channel can be monitored by reading MDIO register 4/5.24.3:0.
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