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TLK3134_1 Datasheet, PDF (71/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver
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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
Table 2-96. SERDES_RX0_CONFIG(1)
BIT(s)
4/5.36866.15:12
4/5.36866.11:9
4/5.36866.8
4/5.36866.7:6
4/5.36866.5:4
4/5.36866.3:2
4/5.36866.1
4/5.36866.0
ADDRESS: 0x9002
DEFAULT: 0x0001
NAME
DESCRIPTION
EQUALIZER
Adaptive equalization control
0000 = Adaptive equalization disabled. Equalizer provides flat response
at maximum gain.
0001 = Full adaptive equalization
0010 to 1111 = Reserved
CDR
Clock data recovery algorithm selection
INVPAIR
1 = Inverts polarity of RXP and RXN
LOS
00 = Loss of signal detection disabled
01 = Reserved
10 = Loss of signal detection enabled with threshold in the range of
85-175 mVdfpp.
11 = Reserved.
ALIGN
Receiver symbol alignment selection
00 = Alignment disabled.
01 = Comma alignment enabled
10 = Symbol alignment will be performed by one bit position when this
mode is selected (i.e ALIGN changes from 00 to 10)
11= Reserved
TERM
Receive Termination selection
00 = Common point connected to VDDT (For DC Coupled Systems)
01 = Common point set to 0.8 VDDT (For AC Coupled Systems)
10 = Reserved
11 = Reserved
ENTEST
1= Enables test modes specified in TESTCFG (Register 0x9012)
ENRX
1 = Enables receiver
0 = Disables receiver
(1) These are SERDES receiver control bits for channel 0.
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
BIT(s)
4/5.36868.15:12
4/5.36868.11:9
4/5.36868.8
4/5.36868.7:6
4/5.36868.5:4
4/5.36868.3:2
4/5.36868.1
Table 2-97. SERDES_RX1_CONFIG(1)
ADDRESS: 0x9004
DEFAULT: 0x0001
NAME
DESCRIPTION
EQUALIZER
Adaptive equalization control
0000 = Adaptive equalization disabled. Equalizer provides flat response
at maximum gain.
0001 = Full adaptive equalization
0010 to 1111 = Reserved
CDR
Clock data recovery algorithm selection
INVPAIR
1 = Inverts polarity of RXP and RXN
LOS
00 = Loss of signal detection disabled
01 = Reserved
10 = Loss of signal detection enabled with threshold in the range of
85-175 mVdfpp.
11 = Reserved.
ALIGN
Receiver symbol alignment selection
00 = Alignment disabled.
01 = Comma alignment enabled
10 = Symbol alignment will be performed by one bit position when this
mode is selected (i.e ALIGN changes from 00 to 10)
11= Reserved
TERM
Receive Termination selection
00 = Common point connected to VDDT (For DC Coupled Systems)
01 = Common point set to 0.8 VDDT (For AC Coupled Systems)
10 = Reserved
11 = Reserved
ENTEST
1= Enables test modes specified in TESTCFG (Register 0x9012)
ACCESS
RW
RW
RW
RW
RW
RW
RW
(1) These are SERDES receiver control bits for channel 1.
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