TLK3134_1 Datasheet, PDF (30/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
2.7.9 RNBI Mode (Reduced Nine Bit Interface)
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DATA CHANNEL
NUMBER
Channel 0
Channel 1
Channel 2
Channel 3
Table 2-12. RNBI – Lane To Functional Pin Mapping
TRANSMIT DATA 5 BITS
(INPUT)
TXD_[4:0]
TXD_[12:8]
TXD_[20:16]
TXD_[28:24]
RECEIVE DATA 5 BITS
(OUTPUT)
RXD_[4:0]
RXD_[12:8]
RXD_[20:16]
RXD_[28:24]
TRANSMIT CLOCK
(INPUT)
TXCLK_[0]
TXCLK_[1]
TXCLK_[2]
TXCLK_[3]
RECEIVE CLOCK
(OUTPUT)
RXCLK_[0]
RXCLK_[1]
RXCLK_[2]
RXCLK_[3]
TXCLK_[0]
TXD_[4:0]
DDR Source Centered Timing
(Nibble Order = 1 Default)
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
TXCLK_[0]
TXD_[4:0]
DDR Source Centered Timing
(Nibble Order = 0)
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
RXCLK_[0]
RXD_[4:0]
TXCLK_[0]
TXD_[4:0]
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
DDR Source Aligned Timing
(Nibble Order = 1 Default)
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
RXCLK_[0]
RXD_[4:0]
TXCLK_[0]
TXD_[4:0]
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
DDR Source Aligned Timing
(Nibble Order = 0)
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
RXCLK_[0]
RXD_[4:0]
Data0[4:0] =
{Data Byte[4:0]}
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
RXCLK_[0]
RXD_[4:0]
Data0[8:5] =
{Control Bit, Data
Byte[7:5]}
Data0[4:0] =
{Data Byte[4:0]}
Figure 2-15. RNBI – Individual Channel Byte Ordering – Channel 0 Example
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Detailed Description
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