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TLK3134_1 Datasheet, PDF (100/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver
TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
• Ensure CODE primary input pin is high.
– Reset Device:
• Issue a hard or soft reset (RST_N asserted –or- Write 1 to 0.15)
– Select single ended or differential REFCLK input:
• If Single Ended REFCLK used - Write 2’b01 to 4/5.37120.15:14
• If Differential REFCLK used – Write 2’b00 to 4/5.37120.15:14
– Select SERDES TX Reference Clock Input:
• If Single Ended REFCLK used - Write 2’b10 to 4/5.37120.11:10
• If Differential REFCLK used – Write 2’b11 to 4/5.37120.11:10
– Select SERDES RX Reference Clock Input:
• If Single Ended REFCLK used - Write 2’b10 to 4/5.37120.9:8
• If Differential REFCLK used – Write 2’b11 to 4/5.37120.9:8
– Ensure a legal reference clock operation frequency is selected based on Appendix A, and provision
control settings accordingly. It is also possible to use the Jitter Cleaner during these tests, and the
user should consult Appendix A for further Jitter Cleaner provisioning details.
– Enable Encoder/Decoder
• Write 1’b1 to 17.2
– Issue Datapath Reset:
• Write 1’b1 to 16.11
– Select Test Pattern:
• If CRPAT Long Pattern is desired:
– Write 3’b011 to 16.2:0
• If CRPAT Short Pattern is desired:
– Write 3’b100 to 16.2:0
– Enable Test Pattern Generation:
• Write 1’b1 to 16.4
– Clear Counters:
• Read 23.15:0 and 24.15:0 and discard the values.
– Enable Test Pattern Verification:
• Write 1’b1 to 16.3
– Verify Test In Progress:
• Poll 21.0 asserted.
– The pattern verification is now in progress.
– Verify Error Free Operation (as many times as desired during the duration of the test period):
• Read 23.15:0, and verify 16’h0000 is read to confirm error free operation.
• Read 24.15:0, and verify 16’h0000 is read to confirm error free operation.
If more than one test is specified results are unpredictable.
If another test type is desired, begin at the first step of that procedure.
100 Device Reset Requirements/Procedure
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