TLK3134_1 Datasheet, PDF (58/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
Table 2-49. LANE_2_CODE_ERROR_COUNT⁽¹⁾
BIT(s)
4/5.32786.15:0
ADDRESS: 0x8012
DEFAULT: 0xFFFD
NAME
DESCRIPTION
Lane 2 Code Error
Counter
Output 16-bit counter for invalid code group found in lane 2. Invalid code
group is detected when the 8B10B decoder cannot decode the received
code word.
ACCESS
RO/COR
(1) Counter will increment by 1 when code word error is found on the corresponding lane and when all the lanes are aligned (align_status
should be high). Counter will hold on to its value when align_status goes low or when the counter reaches its maximum value. It will be
cleared when it is read.
Table 2-50. LANE_3_CODE_ERROR_COUNT⁽¹⁾
BIT(s)
4/5.32787.15:0
ADDRESS: 0x8013
DEFAULT: 0xFFFD
NAME
DESCRIPTION
Lane 3 Code Error
Counter
Output 16-bit counter for invalid code group found in lane 3. Invalid code
group is detected when the 8B10B decoder cannot decode the received
code word.
ACCESS
RO/COR
(1) Counter will increment by 1 when code word error is found on the corresponding lane and when all the lanes are aligned (align_status
should be high). Counter will hold on to its value when align_status goes low or when the counter reaches its maximum value. It will be
cleared when it is read.
BIT(s)
4/5.32788.11:9
4/5.32788.8:6
4/5.32788.5:3
4/5.32788.2:0
Table 2-51. RX_CHANNEL_SYNC_STATE
ADDRESS: 0x8014
NAME
Channel synchronization FSM state for lane 0
Channel synchronization FSM state for Lane 1
Channel synchronization FSM state for Lane 2
Channel Synchronization FSM state for Lane 3
DEFAULT: 0x0000
DESCRIPTION
Current state of sync state machine in lane 0
Current state of sync state machine in lane 1
Current state of sync state machine in lane 2
Current state of sync state machine in lane 3
ACCESS
RO
BIT(s)
4/5.32789.15:12
4/5.32789.0
Table 2-52. RX_LANE_ALIGN_STATUS
ADDRESS: 0x8015
DEFAULT: 0x0000
NAME
DESCRIPTION
Align state
Current lane alignment FSM state
Lane Alignment FIFO Collision status for lane alignment FIFO. When high, indicates that there
collision
is collision error in lane alignment FIFO.
ACCESS
RO
RO/LH
BIT(s)
4/5.32790.11
Table 2-53. RX_CHANNEL_SYNC_STATUS
ADDRESS: 0x8016
DEFAULT: 0x0000
NAME
DESCRIPTION
Channel Synchronization status for all 1 = Channel synchronization is achieved in all lanes.
lanes
0 = Channel synchronization is lost in one or more lanes
ACCESS
RO/LL
BIT(s)
4/5.32791. 3
4/5.32791. 2
4/5.32791. 1
Table 2-54. BIT_ORDER
ADDRESS: 0x8017
DEFAULT: 0x0005
NAME
DESCRIPTION
XGMII RX bit order
When high, reverses the order of bits in the parallel data sent from XAUI RX
for each lane. (Default 1’b0)
XAUI RX bit order
When high, reverses the order of bits in the parallel data received from
SERDES macros for XAUI RX for each lane. (Default 1’b1)
XGMII TX bit order
When high, reverses the order of bits in the parallel data received from the
XGMII interface each lane. (Default 1’b0)
ACCESS
RW
RW
RW
58
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