TLK3134_1 Datasheet, PDF (2/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
Contents
1 Introduction ....................................................................................................................... 13
1.1 Features ..................................................................................................................... 13
1.2 Applications ................................................................................................................. 13
1.3 Pin Out....................................................................................................................... 13
1.4 Description .................................................................................................................. 14
2 Detailed Description ........................................................................................................... 16
2.1 Clocking Modes............................................................................................................. 16
2.2 Operating Frequency Range.............................................................................................. 16
2.3 CPRI Latency Support..................................................................................................... 17
2.4 Powerdown Mode .......................................................................................................... 17
2.5 Application Examples ...................................................................................................... 17
2.6 Device Operation Modes .................................................................................................. 21
2.7 Parallel Interface Modes - Detailed Description........................................................................ 22
2.7.1 XAUI/10GFC Mode.............................................................................................. 22
2.7.2 RGMII Mode (Reduced Gigabit Media Independent Interface)............................................ 23
2.7.3 RTBI Mode (Reduced Ten Bit Interface) ..................................................................... 24
2.7.4 TBI Mode (Ten Bit Interface)................................................................................... 25
2.7.5 GMII Mode (Gigabit Media Independent Interface) ......................................................... 26
2.7.6 EBI Mode (Eight Bit Interface) ................................................................................. 27
2.7.7 REBI Mode (Reduced Eight Bit Interface) ................................................................... 28
2.7.8 NBI Mode (Nine Bit Interface Mode) .......................................................................... 29
2.7.9 RNBI Mode (Reduced Nine Bit Interface) .................................................................... 30
2.7.10 TBID Mode (Ten Bit Interface DDR) .......................................................................... 31
2.7.11 NBID Mode (Nine Bit Interface DDR) ......................................................................... 32
2.7.12 Parallel Interface Clocking Modes............................................................................. 33
2.7.13 Parallel Interface Data .......................................................................................... 34
2.7.14 Transmission Latency........................................................................................... 34
2.7.15 Channel Clock to Serial Transmit Clock Synchronization.................................................. 35
2.7.16 Data Reception Latency ........................................................................................ 35
2.7.17 8B/10B Encoder ................................................................................................. 35
2.7.18 Comma Detect and 8B/10B Decoding........................................................................ 37
2.7.19 Channel Initialization and Synchronization .................................................................. 37
2.7.20 Channel State Descriptions: ................................................................................... 38
2.7.21 End of Packet Error Detection ................................................................................. 39
2.7.22 Fault Detection and Reporting ................................................................................. 39
2.7.23 Receive Synchronization and Skew Compensation ........................................................ 40
2.7.24 Column State Descriptions: .................................................................................... 41
2.7.25 Inter-Packet Gap Management ................................................................................ 42
2.7.26 Clock Tolerance Compensation (CTC) ....................................................................... 44
2.7.27 Parallel to Serial ................................................................................................. 46
2.7.28 Serial to Parallel ................................................................................................. 46
2.7.29 High Speed CML Output ....................................................................................... 46
2.7.30 High Speed Receiver ........................................................................................... 48
2.7.31 Loopback ......................................................................................................... 48
2.7.32 Link Test Functions ............................................................................................. 48
2.7.33 MDIO Management Interface .................................................................................. 48
2.7.34 MDIO Protocol Timing .......................................................................................... 49
2.7.35 Clause 22 Indirect Addressing................................................................................. 50
2.8 Programmers Reference .................................................................................................. 52
2.8.1 10G XAUI Programmers Reference (ST = 0)................................................................ 52
2.9 1G Programmers Reference.............................................................................................. 63
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Contents
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