TLK3134_1 Datasheet, PDF (80/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
Table 2-122. JC_RXB_OUTPUT_CLK_DIV_CONTROL
BIT(s)
ADDRESS: 0x9105
NAME
4/5.37125.14:8 RXB_DIV[6:0]
4/5.37125.7 OUTDIV_EN
4/5.37125.6:0 RXTX_DIV[6:0]
DEFAULT: 0x0E8E
DESCRIPTION
Receive Byte Clock Output Divider Value. This divider value is always
provisioned with the same value as RXTX_DIV[6:0]. See Figure 1-3, and
Appendix A for provisioning details. This value is only used when the jitter
cleaner is used to source the receive parallel interface output clock. Legal
programmed values are greater than or equal to 6
1 = Enables output divider (RXTX_DIV)
0 = Disables output divider
RX/TX SERDES Output Divider Value
See Figure 1-3, and Appendix A for provisioning details Legal
programmed values are greater than or equal to 6
ACCESS
RW
RW
RW
Table 2-123. JC_CHARGE_PUMP_ CONTROL⁽¹⁾
ADDRESS: 0x9106
BIT(s)
NAME
4/5.37126.15:14 CP_BUF_CTRL[1:0]
4/5.37126.13:0 CP_CTRL[13:0]
DEFAULT: 0x00C0
DESCRIPTION
Charge pump buffer control
Charge pump control. When JC PLL is used, CP_CTRL[13:0] values
need to be set according to FB_DIV[6:0] range. Refer Table 2-124:
Charge Pump Control Setting (CP_CTRL)
ACCESS
RW
(1) When JC PLL is used, this register value should be set according to the values specified in Charge Pump Control Setting Table
Table 2-124. Charge Pump Control Setting (CP_CTRL)
FB DIV VALUE RANGE
(4/5.37124[6:0]) (IN DECIMAL)
1 - 15
16 - 18
19 - 30
31 - 33
34 - 45
46 - 53
54 - 59
60 - 68
69 - 77
78 - 85
86 - 88
89 - 91
92 - 99
100 - 107
108 - 113
114 - 127
JC_CHARGE_PUMP_ CONTROL SETTING
(4/5. 37126 [15:0])
0x00FF
0x00C1
0x0081
0x017F
0x017D
0x011F
0x0151
0x0121
0x01C3
0x0101
0x02FB
0x0183
0x0237
0x0181
0x0261
0x0215
80
Detailed Description
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