TLK3134_1 Datasheet, PDF (23/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
2.7.2 RGMII Mode (Reduced Gigabit Media Independent Interface)
DATA
CHANNEL
NUMBER
Channel 0
Channel 1
Channel 2
Channel 3
Table 2-5. RGMII – Lane To Functional Pin Mapping
TX_EN/TX_ER
CONTROL BIT
(INPUT)
TXD_[4]
TXD_[12]
TXD_[20]
TXD_[28]
TRANSMIT
DATA NIBBLE
(INPUT)
TXD_[3:0]
TXD_[11:8]
TXD_[19:16]
TXD_[27:24]
RX_DV/RX_ER
CONTROL BIT
(OUTPUT)
RXD_[4]
RXD_[12]
RXD_[20]
RXD_[28]
RECEIVE
CONTROL
NIBBLE
(OUTPUT)
RXD_[3:0]
RXD_[11:8]
RXD_[19:16]
RXD_[27:24]
TRANSMIT
CLOCK
(INPUT)
TXCLK_[0]
TXCLK_[1]
TXCLK_[2]
TXCLK_[3]
RECEIVE
CLOCK
(OUTPUT)
RXCLK_[0]
RXCLK_[1]
RXCLK_[2]
RXCLK_[3]
TXCLK_[0]
TXD_[4:0]
DDR Source Centered Timing
Nibble Order = 1 (Default)
{TX_EN,Data0[3:0]}
{TX_EN^TX_ER,
Data0[7:4]}
{TX_EN,Data1[3:0]}
{TX_EN^TX_ER,
Data1[7:4]}
Note: If Nibble Order = 0, the picture is
the same except that
{TX_EN,DataN[3:0]} and
{TX_EN^TX_ER,DataN[7:4]} swap
locations.
RXCLK_[0]
RXD_[4:0]
{RX_DV,Data0[3:0]}
{RX_DV^RX_ER,
Data0[7:4]}
{RX_DV,Data1[3:0]}
{RX_DV^RX_ER,
Data1[7:4]}
TXCLK_[0]
TXD_[4:0]
DDR Source Aligned Timing
Nibble Order = 1 (Default)
{TX_EN,Data0[3:0]}
{TX_EN^TX_ER,
Data0[7:4]}
{TX_EN,Data1[3:0]}
{TX_EN^TX_ER,
Data1[7:4]}
Note: If Nibble Order = 0, the picture is
the same except that
{RX_DV,DataN[3:0]} and
{RX_DV^RX_ER,DataN[7:4]} swap
locations.
Note: If Nibble Order = 0, the picture is
the same except that
{TX_EN,DataN[3:0]} and
{TX_EN^TX_ER,DataN[7:4]} swap
locations.
RXCLK_[0]
RXD_[4:0]
{RX_DV,Data0[3:0]}
{RX_DV^RX_ER,
Data0[7:4]}
{RX_DV,Data1[3:0]}
{RX_DV^RX_ER,
Data1[7:4]}
Note: If Nibble Order = 0, the picture is
the same except that
{RX_DV,DataN[3:0]} and
{RX_DV^RX_ER,DataN[7:4]} swap
locations.
Figure 2-8. RGMII – Individual Channel Byte Ordering – Channel 0 Example
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