TLK3134_1 Datasheet, PDF (85/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
Table 2-144. HSTL_OUTPUT_VTP_CONTROL (continued)
BIT(s)
4/5.37635.11:9
4/5.37635.7:5
4/5.37635.3
ADDRESS: 0x9303
NAME
O_VTP_DRIVE[2:0]
O_FILTER_CONTROL[2:0]
O_LOCK
DEFAULT: 0x0640
DESCRIPTION
Drive strength control for HSTL output cells
3’b000 = 30 % drive strength increase
3’b001 = 20% drive strength increase
3’b010 = 10% drive strength increase
3’b011 = Normal drive strength(default)
3’b100 = 10% drive strength decrease
3’b101 = 20% drive strength decrease
3’b110 = 30% drive strength decrease
3’b111 = 40% drive strength decrease
Filter Control
3’b000 = Impedance change filtering off
3’b001 = Update on 2 consecutive update requests
3’b010 = Update on 3 consecutive update requests(default)
3’b011 = Update on 4 consecutive update requests
3’b100 = Update on 5 consecutive update requests
3’b101 = Update on 6 consecutive update requests
3’b110 = Update on 7 consecutive update requests
3’b111 = Update on 8 consecutive update requests
Impedance Lock Control
When set, disables dynamic impedance control updates for HSTL output
cells
ACCESS
RW
RW
RW
BIT(s)
4/5.37636.15
4/5.37636.14
4/5.37636.11
4/5.37636.7
4/5.37636.3
4/5.37636.2
Table 2-145. HSTL_GLOBAL_CONTROL
ADDRESS: 0x9304
NAME
HSTL power down control
HSTL Retrain
HSTL_CLK_EN
Voltage reference selection
VTP POWERSAVE
GP 3-state Control
DEFAULT: 0x0088
DESCRIPTION
When set, triggers HSTL power down sequence and places all HSTL cells
in power down state.
When set, triggers retraining of all HSTL inputs and outputs to match the
impedance. Retraining is triggered only when this bit value goes from 0 to
1.
HSTL impedance control clock (CLK2X) selection
1 = Uses MDC (MDIO clock) as CLK2X
0 = Uses clock generated from Jitter cleaner as CLK2X
1 = Internal voltage reference used for HSTL input signals
0 = External voltage reference used for HSTL input signals
When set, enables power save mode on HSTL VTP controllers
When set, 3-states GP outputs
ACCESS
RW
RW
RW
RW
RW
RW
BIT(s)
4/5.37888.15
4/5.37888.14
4/5.37888.13:8
ADDRESS: 0x9400
NAME
Lock_en
Write_en
Delay_sel[5:0]
4/5.37888.7:5 Offset[2:0]
4/5.37888.3 Filter_en
Table 2-146. TX0_DLL_CONTROL
DEFAULT: 0x0008
DESCRIPTION
For TI use only
For TI use only
DLL delay control. For TI use only
Phase shift control. Adds or removes delay element. Each delay element
is 0.15ns. Refer Table 2-154: DLL Offset Control
When asserted, the internal filter is used to reduce the cycle to cycle jitter
of the output clock.
ACCESS
RW
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Detailed Description
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