TLK3134_1 Datasheet, PDF (132/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
CPRI Mode - Legal Clocking Mode Settings
TLK3134 Jitter SERDES SERDES Serial Data Rate = f(SPEED[1:0]) (Mbps)
REFCLK Cleaner REFCLK PLL Full (00) Half (01) Qrtr. (10)
Input (MHz) Multiplier Input (MHz) Multiplier
61.44000 OFF 61.44000
20 2457.600 1228.800 614.400
61.44000 0.25 15.36000
61.44000
0.5
30.72000
61.44000
1
61.44000
20 2457.600 1228.800 614.400
61.44000
2
122.88000 10 2457.600 1228.800 614.400
122.88000 OFF 122.88000 10 2457.600 1228.800 614.400
122.88000 0.25 30.72000
122.88000 0.5 61.44000
20 2457.600 1228.800 614.400
122.88000
1
122.88000 10 2457.600 1228.800 614.400
122.88000
2
245.76000
5
2457.600 1228.800 614.400
245.76000 OFF 245.76000
5
2457.600 1228.800 614.400
245.76000 0.25 61.44000
20 2457.600 1228.800 614.400
245.76000 0.5 122.88000 10 2457.600 1228.800 614.400
245.76000
1
245.76000
5
2457.600 1228.800 614.400
Figure A-6. Reference Clock Selection – CPRI Mode
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Nine/Ten Bit SERDES Mode - Clock Range Support (RATE[1:0] == 00) (Full)
REFCLK
Jitter SERDES REFCLK SERDES Serial Data Rate (Mbps)
Minimum Maximum Cleaner Minimum Maximum PLL
Full
(MHz) (MHz) Multiplier (MHz) (MHz) Multiplier Minimum Maximum
200.0000 375.0000 OFF 200.0000 375.0000
5
2000.00 3750.00
100.0000 187.5000 OFF 100.0000 187.5000 10
2000.00 3750.00
50.0000 93.7500 OFF 50.0000 93.7500
20
2000.00 3750.00
800.0000 ######## 0.25 200.0000 375.0000
5
2000.00 3750.00
400.0000 850.0000 0.25 100.0000 212.5000 10
2000.00 4250.00
200.0000 375.0000 0.25 50.0000 93.7500
20
2000.00 3750.00
400.0000 750.0000 0.5 200.0000 375.0000
5
2000.00 3750.00
200.0000 375.0000 0.5 100.0000 187.5000 10
2000.00 3750.00
100.0000 187.5000 0.5
50.0000 93.7500
20
2000.00 3750.00
200.0000 375.0000
1
200.0000 375.0000
5
2000.00 3750.00
100.0000 187.5000
1
100.0000 187.5000 10
2000.00 3750.00
50.0000 93.7500
1
50.0000 93.7500
20
2000.00 3750.00
100.0000 187.5000
2
200.0000 375.0000
5
2000.00 3750.00
50.0000 93.7500
2
100.0000 187.5000 10
2000.00 3750.00
25.0000 46.8750
2
50.0000 93.7500
20
2000.00 3750.00
Figure A-7. Reference Clock Selection – 9/10 Bit SERDES Mode – Full Rate (SPEED[1:0] == 00)
132 APPENDIX A – Frequency Ranges Supported
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