TLK3134_1 Datasheet, PDF (60/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
BIT(s)
4/5.32796.15:0
Table 2-59. RX_CTC_DELETE_COUNT
ADDRESS: 0x801C
NAME
DESCRIPTION
Idle delete count
Counter for number of idle deletions
DEFAULT: 0xFFFD
ACCESS
RO/COR
BIT(s)
4/5.32797.3
4/5.32797.2
4/5.32797.1
4/5.32797.0
Table 2-60. DATA_DOWN
ADDRESS: 0x801D
DEFAULT: 0x0000
NAME
DESCRIPTION
Lane 3 data down
Lane 2 data down
Lane 1 data down
Lane 0 data down
When high, indicates that link for the corresponding lane was inactive (data
did not toggle) for 4095 cycles of recovered clock from serial input data
The recovered clock is generated internally by the PLL from the 156Mhz
Reference clock.
ACCESS
RO/COR
BIT(s)
4/5.32798.15
4/5.32798.14
4/5.32798.11
4/5.32798.10
4/5.32798.9
4/5.32798.8
4/5.32798.7
4/5.32798.3
Table 2-61. RX_MODE_CONTROL
ADDRESS: 0x801E
DEFAULT: 0x0000
NAME
DESCRIPTION
RX CTC disable
When set, disables clock tolerance compensation on the RX
side. (Default 1’b0)
IPG Checker bypass
When set, disables the replacement of /A/K/R/ into Idles and
also bypasses end-of-packet error checking. (Default 1’b0)
Lane 3 8B/10B decoder bypass
Lane 2 8B/10B decoder bypass _{When set, disables the XAUI 8B/10B decoding for the}
Lane 1 8B/10B decoder bypass ^{corresponding lane. (Default 1’b0)}
Lane 0 8B/10B decoder bypass
Consider sequence column part
of IPG
When high, sequence columns are counted as part of IPG.
When low, sequence columns are not counted as IPG (Default
1’b0)
RX Lane align bypass enable When set, enables lane alignment bypass on the RX side
ACCESS
RW
RW
RW
RW
RW
BIT(s)
4/5.32799. 7
4/5.32799. 6
4/5.32799. 5
4/5.32799. 4
4/5.32799. 3
4/5.32799. 2
4/5.32799. 1
4/5.32799. 0
Table 2-62. CLOCK_DOWN_STATUS
ADDRESS: 0x801F
NAME
Lane 3 clock 312 down
Lane 2 clock 312 down
Lane 1 clock 312 down
Lane 0 clock 312 down
Lane 3 clock 156 down
Lane 2 clock 156 down
Lane 1 clock 156 down
Lane 0 clock 156 down
DEFAULT: 0x0000
DESCRIPTION
When high, indicates that serial clock generated by SERDES TX
is down on the corresponding lane for 255 or more cycles. The
detection is done on the transmit side.
When high, indicates that 156MHz XGMII clock is down on the
corresponding lane for 255 or more cycles. The detection is done
on the transmit side
ACCESS
RO/LH
RO/LH
BIT(s)
4/5.32800. 15
Table 2-63. DATAPATH_RESET_CONTROL
ADDRESS: 0x8020
DEFAULT: 0x0000
NAME
DESCRIPTION
XAUI datapath reset
When set, resets XAUI data path but does not reset any R/W registers.
(Default 1’b0)
ACCESS
RW/SC
60
Detailed Description
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