TLK3134_1 Datasheet, PDF (3/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
2.10 Top Level Programmers Reference ..................................................................................... 68
3 Device Reset Requirements/Procedure ................................................................................ 91
3.1 XAUI MODE (XGMII) ...................................................................................................... 91
3.2 Gigabit Ethernet Mode (RGMII) .......................................................................................... 94
3.3 Jitter Test Pattern Generation and Verification Procedures .......................................................... 97
3.4 PRBS Test Generation and Verification Procedures................................................................. 101
3.5 Signal Pin Description.................................................................................................... 104
4 Electrical Specifications .................................................................................................... 112
4.1 ABSOLUTE MAXIMUM RATINGS ..................................................................................... 112
4.2 RECOMMENDED OPERATING CONDITIONS ...................................................................... 112
4.3 REFERENCE CLOCK TIMING REQUIREMENTS (REFCLKP/N) ................................................. 113
4.4 REFERENCE CLOCK ELECTRICAL CHARACTERISTICS (REFCLKP/N) ...................................... 113
4.5 SINGLE ENDED REFERENCE CLOCK ELECTRICAL CHARACTERISTICS (REFCLK)...................... 113
4.6 JITTER CLEANER TIMING PARAMETERS .......................................................................... 113
4.7 LVCMOS ELECTRICAL CHARACTERISTICS ....................................................................... 114
4.8 MDIO ELECTRICAL CHARACTERISTICS ........................................................................... 114
4.9 HSTL SIGNALS (VDDQ = 1.5/1.8 V) ELECTRICAL CHARACTERISTICS....................................... 114
4.10 SERIAL TRANSMITTER/RECEIVER CHARACTERISTICS........................................................ 115
4.10.1 Parameter Measurement ..................................................................................... 116
4.11 HSTL Output Switching Characteristics (DDR Timing Mode Only) ................................................ 120
4.12 HSTL Output Switching Characteristics (SDR Timing Mode Only) ................................................ 121
4.13 HSTL (DDR Timing Mode Only) Input Timing Requirements....................................................... 122
4.14 HSTL (SDR Timing Mode Only) Input Timing Requirements ....................................................... 123
4.15 MDIO Timing Requirements Over Recommended Operating Conditions......................................... 124
4.16 JTAG Timing Requirements Over Recommended Operating Conditions ......................................... 125
Package Dissipation Rating ............................................................................................. 127
A APPENDIX A – Frequency Ranges Supported ...................................................................... 129
A.1 Recovered Byte Clock Jitter Cleaner Mode: .......................................................................... 144
B APPENDIX B – Jitter Cleaner PLL External Loop Filter .......................................................... 146
C APPENDIX C – Device Test Mode ....................................................................................... 147
Contents
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