TLK3134_1 Datasheet, PDF (105/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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SIGNAL
CODE
TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
LOCATION
M3
Table 3-1. Global Signals (continued)
VOLTAGE
VDDO
TYPE
2.5 V LVCMOS
Input
DESCRIPTION
Code Enable. This signal selects different functionality based on the
setting of the ST primary chip input pin.
ST=0:
This signal is logically OR’d with the XAUI_ORDER register bit (Register
Bit 32809.15). XAUI applications can either tie this input signal high
(preferred) or tie this signal low (must program the XAUI_ORDER register
bit after device reset to high if CODE is tied off low). 10GFC applications
must tie this signal low.
ST=1:
This signal is logically OR’d with the PCS_EN register bit (Register Bit
17.3). RGMII/GMII applications can either tie this input signal high
(preferred) or tie this signal low (must program the PCS_EN 17.3 register
bit after device reset to high if CODE is tied off low). Non RGMII/GMII
applications must tie this input signal low.
SIGNAL
TDI
TDO
TMS
TCK
TRST_N
LOCATION
N13
R15
P15
P17
N15
VOLTAGE
VDDO
VDDO
VDDO
VDDO
VDDO
Table 3-2. JTAG Signals
TYPE
DESCRIPTION
2.5 V LVCMOS
Input (Internal
Pullup)
JTAG Input Data. TDI is used to serially shift test data and test instructions
into the device during the operation of the test port.
2.5 V LVCMOS
Output
JTAG Output Data. TDO is used to serially shift test data and test instructions
out of the device during operation of the test port. When the JTAG port is not
in use, TDO is in a high impedance state.
2.5 V LVCMOS
Input (Internal
Pullup)
JTAG Mode Select. TMS is used to control the state of the internal test-port
controller.
2.5 V LVCMOS JTAG Clock. TCK is used to clock state information and test data into and out
Input
of the device during the operation of the test port.
2.5 V LVCMOS
Input (Internal
Pullup)
JTAG Test Reset. TRST_N is used to reset the JTAG logic into system
operational mode.
SIGNAL
MDC
MDIO
PRTAD[4:
0]
LOCATION
T16
U16
N5, N4, N3,
N2, T1
VOLTAGE
VDDM
VDDM
VDDO
Table 3-3. MDIO Related Signals
TYPE
1.2 V OR 2.5 V
LVCMOS Input
1.2 V OR 2.5 V
LVCMOS Input/
Output
2.5 V LVCMOS
Input
DESCRIPTION
Management Interface Clock This clock is used to sample the MDIO signal.
Management Interface Data This bidirectional data line for MDIO Port is
sampled on the rising edge of MDC.
THIS SIGNAL MUST BE EXTERNALLY PULLED UP TO VDDM. Consult
IEEE802.3 Clause 22/45 for an appropriate resistance value.
Port Address Used to select the Device Id/Port ID in Clause 22/Clause 45
MDIO modes.
ST=0 (Clause 45 Mode):
If PRTAD[0] is a 0, then a PHY device is selected for XAUI/10GFC register
accesses (4.xxxxx.x).
If PRTAD[0] is a 1, then a DTE device is selected for XAUI/10GFC register
accesses (5.xxxxx.x).
PRTAD[4:1] selects the Clause 45 port address (TLK3134 must be located
on even boundaries since the lowest port address bit determines DTE/PHY,
and is used as a device address instead of port address).
ST=1 (Clause 22 Mode):
PRTAD[4:2] selects a block of four sequential Clause 22 port addresses.
Each channel is implemented as a different port address, and can be
accessed by setting the appropriate port address field within the Clause 22
MDIO transaction. PRTAD[1:0] pins are not used in Clause 22 mode.
Channel 0 responds to port address 0 within the block of four port addresses.
Channel 1 responds to port address 1 within the block of four port addresses.
Channel 2 responds to port address 2 within the block of four port addresses.
Channel 3 responds to port address 3 within the block of four port addresses.
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Device Reset Requirements/Procedure 105