TLK3134_1 Datasheet, PDF (68/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
BIT(s)
27.15
27.14:12
Table 2-88. PHY_TEST_MODE_CONTROL
ADDRESS: 0x1B
NAME
Global write
Test Mux Select
DEFAULT: 0x7000
DESCRIPTION
When written as 1 the settings in 27.14:12 will affect all channels of one
device simultaneously.
When written as 0 the settings in 27.14:12 are only valid for the
addressed channel.
This value always reads zero.
Mux control to select debug signals onto test mux data pins. For TI test
purposes only
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ACCESS
RW/SC
RW
BIT(s)
28.15
28.13
28:12
Table 2-89. PHY_CHANNEL_STATUS
ADDRESS: 0x1C
DEFAULT: 0x0000
NAME
DESCRIPTION
Signal Detect
When high, indicates that the SERDES detected valid signal.
Encoder Invalid Code When high, indicates that the 1000Base-X encoder received an invalid
Word
control word.
Decoder Invalid Code When high, indicates that the 1000Base-X decoder received an invalid
Word
code word.
ACCESS
RO/LL
RO/LH
BIT(s)
29.15:0
Table 2-90. PHY_PRBS_HIGH_SPEED_TEST_COUNTER
ADDRESS: 0x1D
NAME
PRBS High Speed
Test Counter
DEFAULT: 0xFFFD
DESCRIPTION
This counter reflects errors for PRBS (2^7) test pattern verification .
Counter increments by one for each received character that has error.
This counter saturates at 16’hffff. When read, it resets to zero and
continues to count.
ACCESS
COR
Table 2-91. PHY_EXT_ADDRESS_CONTROL⁽¹⁾
BIT(s)
30.15:0
ADDRESS: 0x1E
NAME
Ext address control
DEFAULT: 0x0000
DESCRIPTION
This register should be written with the extended register address to be
written/read. Contents of address written in this register can be accessed
from Reg 31 (0x1F).
(1) This register is not per channel basis. This register can be accessed through any of the 4 channels.
ACCESS
RW
Table 2-92. PHY_EXT_ADDRESS_DATA⁽¹⁾
BIT(s)
31.15:0
ADDRESS: 0x1F
NAME
Ext address data
register
DEFAULT: 0x0000
DESCRIPTION
This register contains the data associated with the register address
written in Register 30 (0x1E)
(1) This register is not per channel basis. This register can be accessed through any of the 4 channels.
ACCESS
RW
2.10 Top Level Programmers Reference
Following registers can be addressed directly through Clause 45 and indirectly through Clause 22.
68
Detailed Description
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