TLK3134_1 Datasheet, PDF (92/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
– If Single Ended REFCLK used – Write 2’b01 to 4/5.37120.15:14
– If Differential REFCLK used – Write 2’b00 to 4/5.37120.15:14
– Select RXBYTE_CLK (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.13:12
– If Differential REFCLK used – Write 2’b11 to 4/5.37120.13:12
– Select SERDES TX Reference Clock Input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.11:10
– If Differential REFCLK used – Write 2’b11 to 4/5.37120.11:10
– Select SERDES RX Reference Clock Input (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.9:8
– If Differential REFCLK used – Write 2’b11 to 4/5.37120.9:8
– Select HSTL_2X_CLK (Default = Differential)
– If Single Ended REFCLK used – Write 2’b10 to 4/5.37120.5:4
– If Differential REFCLK used – Write 2’b11 to 4/5.37120.5:4
– Write 2’b00 to 4/5.32810.15:14 to select SERDES TX clock as RX_CLK output
– Write 7’h04 to 4/5.37121.6:0 to set HSTL_DIV2 to value of 4.
– Write 16’h0000 to 4/5.36865 SERDES_RATE_CONFIG_TX_RX to set Full Rate
• Mode Control (see Table 2-2)
– Write 1’b1 to 4/5.32809.15 XAUI_ORDER
– Write 1’b0 to 4/5.32808.15 to set source centered data for TX side
– Write 1’b0 to 4/5.32808.11 to set source centered data for RX side
– Write 1’b0 to 4/5.32792.1 to disable XAUI data loop back
– Write 1’b0 to 4/5.32792.0 to disable XGMII data loop back
– Write 1’b0 to 4/5.0.14 to disable loop back mode
– Write 3’b110 to 4/5.36874.11:9 to set lane 0 TX swing setting amplitude to 1250 mVdfpp
– Write 1’b1 to 4/5.36874.8 to set channel 0 TX CM bit
– Write 3’b110 to 4/5.36876.11:9 to set lane 1 TX swing setting amplitude to 1250 mVdfpp
– Write 1’b1 to 4/5.36876.8 to set channel 1 TX CM bit
– Write 3’b110 to 4/5.36878.11:9 to set lane 2 TX swing setting amplitude to 1250 mVdfpp
– Write 1’b1 to 4/5.36878.8 to set channel 2 TX CM bit
– Write 3’b110 to 4/5.36880.11:9 to set lane 3 TX swing setting amplitude to 1250 mVdfpp
– Write 1’b1 to 4/5.36880.8 to set channel 3 TX CM bit
• RX equalization settings
– Write 4’b0001 to 4/5.36866.15:12 to turn on adaptive equalization (4’b0000 is off)
– Write 4’b0001 to 4/5.36868.15:12 to turn on adaptive equalization (4’b0000 is off)
– Write 4’b0001 to 4/5.36870.15:12 to turn on adaptive equalization (4’b0000 is off)
– Write 4’b0001 to 4/5.36872.15:12 to turn on adaptive equalization (4’b0000 is off)
– Write 2’b01 to 4/5.36866.3:2 for AC coupled mode (2’b00 is DC coupled mode)
– Write 2’b01 to 4/5.36868.3:2 for AC coupled mode (2’b00 is DC coupled mode)
– Write 2’b01 to 4/5.36870.3:2 for AC coupled mode (2’b00 is DC coupled mode)
– Write 2’b01 to 4/5.36872.3:2 for AC coupled mode (2’b00 is DC coupled mode)
• TX DLL Offset
– Write 16'h0028 to 4/5.37888 TX0_DLL_CONTROL
– Write 16'h0028 to 4/5.37889 TX1_DLL_CONTROL
– Write 16'h0028 to 4/5.37890 TX2_DLL_CONTROL
– Write 16'h0028 to 4/5.37891 TX3_DLL_CONTROL
• Poll Serdes PLL Status for Locked State
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Device Reset Requirements/Procedure
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