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TLK3134_1 Datasheet, PDF (57/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver
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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
Table 2-44. LANE_1_EOP_ERROR_COUNT(1)
ADDRESS: 0x800D
DEFAULT: 0xFFFD
BIT(s)
NAME
DESCRIPTION
ACCESS
4/5.32781.15:0
Lane 1 end of packet
error counter
End of packet termination error counter for lane 1. End of packet error
for lane 1 is detected on the RX side. It is detected when Terminate
character is in lane 1 and one or both of the following holds:
• Terminate character is not followed by /K/ characters in lanes 2
and 3
• The column following the terminate column is neither ||K|| nor ||A||.
RO/COR
(1) Counter will increment by 1 when EOP error is found on the corresponding lane and when all the lanes are aligned (align_status should
be high). Counter will hold on to its value when align_status goes low or when the counter reaches its maximum value. It will be cleared
when it is read.
Table 2-45. LANE_2_EOP_ERROR_COUNT(1)
ADDRESS: 0x800E
DEFAULT: 0xFFFD
BIT(s)
NAME
DESCRIPTION
ACCESS
4/5.32782.15:0
Lane 2 end of packet
error counter
End of packet termination error counter for lane 2. End of packet error for
lane 2 is detected on the RX side. It is detected when Terminate
character is in lane 2 and one or both of the following holds:
• Terminate character is not followed by /K/ character in lane 3
• The column following the terminate column is neither ||K|| nor ||A||.
RO/COR
(1) Counter will increment by 1 when EOP error is found on the corresponding lane and when all the lanes are aligned (align_status should
be high). Counter will hold on to its value when align_status goes low or when the counter reaches its maximum value. It will be cleared
when it is read.
Table 2-46. LANE_3_EOP_ERROR_COUNT(1)
BIT(s)
4/5.32783.15:0
ADDRESS: 0x800F
DEFAULT: 0xFFFD
NAME
DESCRIPTION
Lane 3 end of packet
error counter
End of packet termination error counter for lane 3. End of packet error for
lane 3 is detected on the RX side. It is detected when Terminate
character is in lane 3 and the column following the terminate column is
neither ||K|| nor ||A||.
ACCESS
RO/COR
(1) Counter will increment by 1 when EOP error is found on the corresponding lane and when all the lanes are aligned (align_status should
be high). Counter will hold on to its value when align_status goes low or when the counter reaches its maximum value. It will be cleared
when it is read.
Table 2-47. LANE_0_CODE_ERROR_COUNT(1)
BIT(s)
4/5.32784.15:0
ADDRESS: 0x8010
DEFAULT: 0xFFFD
NAME
DESCRIPTION
Lane 0 Code Error
Counter
Output 16-bit counter for invalid code group found in lane 0. Invalid code
group is detected when the 8B10B decoder cannot decode the received
code word.
ACCESS
RO/COR
(1) Counter will increment by 1 when code word error is found on the corresponding lane and when all the lanes are aligned (align_status
should be high). Counter will hold on to its value when align_status goes low or when the counter reaches its maximum value. It will be
cleared when it is read.
Table 2-48. LANE_1_CODE_ERROR_COUNT(1)
BIT(s)
4/5.32785.15:0
ADDRESS: 0x8011
DEFAULT: 0xFFFD
NAME
DESCRIPTION
Lane 1 Code Error
Counter
Output 16-bit counter for invalid code group found in lane 1. Invalid code
group is detected when the 8B10B decoder cannot decode the received
code word.
ACCESS
RO/COR
(1) Counter will increment by 1 when code word error is found on the corresponding lane and when all the lanes are aligned (align_status
should be high). Counter will hold on to its value when align_status goes low or when the counter reaches its maximum value. It will be
cleared when it is read.
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