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TLK3134_1 Datasheet, PDF (122/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver | |||
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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D â MAY 2007 â REVISED JULY 2008
4.13 HSTL (DDR Timing Mode Only) Input Timing Requirements
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN NOM(1)
tsetup
TXDATA setup prior to Source Centered. See Figure 4-9.
TXCLK transition high Note: Input timing reference of VDDQ/2, with ±1 ns/V
or low
rise time on all inputs signals.
0.075 Ã tperiod
thold TXDATA hold after
Source Centered. See Figure 4-9.
0.075 Ã tperiod
TXCLK transition high Note: Input timing reference of VDDQ/2, with ±1 ns/V
or low
rise time on all inputs signals.
tduty TXCLK Duty Cycle
Source Centered
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all inputs signals.
40%
tduty TXCLK Duty Cycle
Source Aligned.
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all inputs signals.
45%
tperiod TXCLK Period
Tfreq TXCLK Frequency
Source Centered and Aligned.
Source Centered and Aligned.
6.25
60 (3)
Tskew
TXCLK rising or falling
to TXDATA valid.
Source Aligned. See Figure 4-10.
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all inputs signals.
â0.175 Ã
tperiod (4)
(1) All typical values are at 25°C and with a nominal supply.
(2) In TBID/NBID Modes Only, the maximum allowed TXCLK period is 33.33 ns.
(3) In TBID/NBID Modes Only, the minimum allowed TXCLK frequency is 30 Mhz.
(4) In TBID/NBID Modes, when the TXCLK is in the 30 â 60 Mhz range, this parameter becomes -0.10 Ã tperiod
(5) In TBID/NBID Modes, when the TXCLK is in the 30â 60 Mhz range, this parameter becomes +0.10 Ã tperiod
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MAX UNIT
ps
ps
60%
55%
16.67 (2)
160
+0.175 Ã
tperiod (5)
ns
MHz
ps
TXCLK
t
VIH(ac)
VDDQ/2
VIL(ac)
tSETUP
tHOLD
tSETUP
tHOLD
VIH(ac)
TXDATA VDDQ/2
VIL(ac)
Figure 4-9. HSTL (DDR Timing Mode Only) Source Centered Data Input Timing Requirements
TXCLK
TXDATA
VOH(ac)
VDDQ/2
VOL(ac)
Tskew
Tskew
VOH(ac)
VDDQ/2
VOL(ac)
Figure 4-10. HSTL (DDR Timing Mode Only) Source Aligned Data Input Timing Requirements
122 Electrical Specifications
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