TLK3134_1 Datasheet, PDF (81/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
Table 2-125. JC_PLL_CONTROL
ADDRESS: 0x9107
DEFAULT: 0x30C4
BIT(s)
NAME
DESCRIPTION
4/5.37127.15 JC_EN_PLL
0 = Disables Jitter Cleaner
1 = Enables Jitter Cleaner
4/5.37127.14:12 VCO_BIAS_CTRL[2:0]
Control bits for VCO tail current
4/5.37127.11:8
VCO_CAPBANK_CTRL[3:0
]
Control bits for VCO band select
4/5.37127.7 DIFFTX_EN
Enable signal for TX differential path
4/5.37127.6 DIFFRX_EN
Enable signal for RX differential path
4/5.37127.5:4 PFD_CTRL[1:0]
Control bits for phase frequency detector
4/5.37127.3 AD_SEL_TST
Control bit to select either digital or analog TST_OUT
4/5.37127.2 REFCLK_CML_EN
Enable signal for CML buffer inside output divider
ACCESS
RW
Table 2-126. JC_TEST_CONTROL_1⁽¹⁾
ADDRESS: 0x9108
BIT(s)
NAME
4/5.37128.15:12 REFCK_DIV_TST[3:0]
4/5.37128.11:8 FB_DIV_TST[3:0]
4/5.37128.7:4 TXRX_DIV_TST[3:0]
4/5.37128.3:2 RXBCLK_DIV_TST[1:0]
DEFAULT: 0x0000
DESCRIPTION
Test bits for Reference divider
Test bits for Feedback divider
Test bits for TXRX output divider. Should be set to 4’b1010 when JC PLL
is used
Test bits for RXBYTECLK divider
(1) This register value should be written 0x00A0 when JC PLL is used
Table 2-127. JC_TEST_CONTROL_2
ADDRESS: 0x9109
BIT(s)
NAME
4/5.37129.15:14 DEL_DIV_TST[1:0]
4/5.37129.13:12 HSTL_DIV_TST[1:0]
4/5.37129.11:10 HSTL_DIV2_TST[1:0]
4/5.37129.9:8 PFD_TST[1:0]
4/5.37129.7:4 CP_TST[3:0]
4/5.37129.3:0 CP_BUF_TST[3:0]
DEFAULT: 0x0000
DESCRIPTION
Test bits for Delay clock divider
Test bits for HSTL VTP divider
Test bits for HSTL VTP 2X divider
Test bits for Phase frequency detector
Test bits for Charge pump
Test bits for Charge pump Buffer
ACCESS
RW
ACCESS
RW
Table 2-128. JC_TI_TEST_CONTROL_1
BIT(s)
4/5.37200.15:8
4/5.37200.7:4
ADDRESS: 0x9150
NAME
CML_BIAS_TST[7:0]
CML_BIAS_CTRL[3:0]
4/5.37200.3 DIFFTX_ENTST
4/5.37200.2 DIFFRX_ENTST
DEFAULT:0x0000
DESCRIPTION
Test bits for Bias generator for CML divider. For TI purposes only.
Control bits for Bias generator for CML divider. For TI purposes only.
Enable for TX clock out from SERDES REFCLK MUX. For TI purposes
only.
Enable for RX clock out from SERDES REFCLK MUX. For TI purposes
only.
ACCESS
RW
Table 2-129. JC_TI_TEST_CONTROL_2
ADDRESS: 0x9151
BIT(s)
NAME
4/5.37201.15:13 VCO_FILCAP_CTRL[2:0]
4/5.37201.12:10 ANA_MUX_CTRL[2:0]
DEFAULT: 0x0000
DESCRIPTION
Control bits for VCO tail current noise filter. For TI purposes only.
Control bits to select the tested signals. For TI purposes only.
ACCESS
RW
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