TLK3134_1 Datasheet, PDF (49/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
In Clause 22 (ST = 1), the top 3 control pins PRTAD[4:2] determine the device port address. In this mode
the 4 individual channels in TLK3134 are classified as 4 different ports. So for any PRTAD[4:2] value there
will be 4 ports per TLK3134. TLK3134 will respond if the 3 MSB’s of PHY address field on MDIO protocol
(PA[4:2]) matches PRTAD[4:2]. 2 LSB’s of PHY address field (PA[1:0]) will determine which channel/port
within TLK3134 to respond.
If PA[1:0] = 2’b00, TLK3134 Channel 0 will respond.
If PA[1:0] = 2’b01, TLK3134 Channel 1 will respond.
If PA[1:0] = 2’b10, TLK3134 Channel 2 will respond.
If PA[1:0] = 2’b11, TLK3134 Channel 3 will respond.
Write transactions which address an invalid register or device or a read only register will be ignored. Read
transactions which address an invalid register will return a 0.
2.7.34 MDIO Protocol Timing
Timing for a Clause 45 address transaction is shown in Figure 2-32. The Clause 45 timing required to
write to the internal registers is shown in Figure 2-33. The Clause 45 timing required to read from the
internal registers is shown in Figure 2-34. The Clause 45 timing required to read from the internal registers
and then increment the active address for the next transaction is shown in Figure 2-35. The Clause 22
timing required to read from the internal registers is shown in Figure 2-36. The Clause 22 timing required
to write to the internal registers is shown in Figure 2-37.
MDC
MDIO
0
0
0
0
PA [4:0]
DA [4:0]
1
0 A15 A0
1
32 "1's"
Preamble
Start
Addr
Code
PHY
Addr
Dev
Addr
Turn
Around
Reg
Addr
Idle
Note that the 1 in the Turn Around section is externally pulled up, and driven to Z by TLK3134
Figure 2-32. CL45 - Management Interface Extended Space Address Timing
MDC
MDIO
0
0
0
1
PA [4:0]
DA [4:0]
1
0 D15 D0
1
32 "1's"
Preamble
Start
Write
Code
PHY
Dev
Turn
Addr
Addr
Around
Data
Idle
Figure 2-33. CL45 – Management Interface Extended Space Write Timing
MDC
MDIO
Pu1
0
0
1
1 _{PA4 PA0 DA4 DA0}
0 D15 D0
32 "1's"
Preamble
Start
Read
Code
PHY
Addr
Dev
Addr
Turn
Around
Data
Figure 2-34. CL45 – Management Interface Extended Space Read Timing
1
Idle
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Detailed Description
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