TLK3134_1 Datasheet, PDF (90/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
BIT(s)
ADDRESS: 0x9800
NAME
4/5.38912:8 DEBUG_SEL_EN
4/5.38912.7 DIG_TST_OUT_EN
4/5.38912.4:0 DEBUG_SEL
Table 2-170. DEBUG_CONTROL
DEFAULT: 0x001F
DESCRIPTION
1 = Sends debug status signals onto debug outputs (GPO)
0 = Debug outputs are tied to 0.
For TI test purposes only
1 = Enables sending DIG TST debug signal onto GPO4
0 = Disables sending DIG TST debug signal onto GPO4.
For TI test purposes only
Debug select bits. For TI test purposes only
ACCESS
RW
BIT(s)
4/5.39168.15
Table 2-171. DUTY_CYCLE_CONTROL
ADDRESS: 0x9900
NAME
Duty Cycle Correction
Bypass
DEFAULT: 0x0000
DESCRIPTION
1 = Bypasses duty cycle corrected RX/TXBCLK. (Duty cycle set to 40-60,
same clocks as SERDES parallel launch and capture clocks)
0 = Uses duty cycle corrected RX/TXBCLK. (Duty cycle set to 50-50, no
phase relationship to SERDES parallel launch and capture clock)(Default)
For TI test purposes only
ACCESS
RW
90
Detailed Description
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