TLK3134_1 Datasheet, PDF (52/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
2.8 Programmers Reference
2.8.1 10G XAUI Programmers Reference (ST = 0)
Following 10G XAUI registers can be addressed only through Clause 45. Primary device input pin “ST”
must be 0 to use Clause 45.
Table 2-19. XS_CONTROL_1⁽¹⁾
BIT(s)
4/5.0.15
4/5.0.14
4/5.0.13
4/5.0.11
4/5.0.6
4/5.0.5:2
ADDRESS: 0x0000
DEFAULT: 0x2040
NAME
DESCRIPTION
Reset
1 = XGXS reset (including all registers)
0 = Normal operation (Default)
Loop Back
1 = Enable loop back mode.
If the device is configured as PHY XS (PRTAD(0) = 0), then
XAUI_DATA_LOOPBACK will be performed (Same as SLOOP).
If the device is configured as DTE XS (PRTAD(0) = 1), then
XGMII_DATA_LOOPBACK will be performed (Same as PLOOP)
0 = Disable loop back mode (Default)
Speed Selection
This bit always reads 1 indicating operation at 10 Gbps and above.
Low Power
1 = Low power mode
0 = Normal operation (Default)
In low power mode all the internal clocks and datapaths are placed in shut
down mode. After de-assertion of this bit, datapath reset (4/5.32800.15)
needs to be performed to achieve proper datapath function. Serdes PLL’s
can be shut down by de-asserting bits 4/5.36864.12 and 4/5.36864.4. Jitter
cleaner PLL can be shut down by de-asserting 4/5.37127.15
Speed Selection
This bit always reads 1 indicating operation at 10Gbps and above.
Speed Selection
These bits always read 0 indicating operation at 10Gbps.
(1) In this section XS refers to either PHY or DTE XS device.
(2) RO: Read-Only, RW: Read-Write, SC: Self-Clearing, LL: Latching-Low, LH: Latching-High, COR: Clear-on-Read
ACCESS ⁽²⁾
RW
SC
RW
RO
RW
RO
BIT(s)
4/5.1.7
4/5.1.2
4/5.1.1
Table 2-20. XS_STATUS_1
ADDRESS: 0x0001
DEFAULT: 0x0082
NAME
DESCRIPTION
Fault
1 = Fault condition detected
(either on TX or RX side. This bit is OR ed version of 4/5.8.10 and 4/5.8.11)
0 = No fault condition detected
XS Transmit Link
Status
1 = XS Transmit link is up.
0 = XS Transmit links is down.
(This bit is latched low version of 4/5.24.12)
Low Power Ability
This bit always reads 1 indicating support for low power mode
ACCESS
RO
RO/LL
RO
BIT(s)
4/5.2.15.0
Table 2-21. XS_DEVICE_IDENTIFIER_1
ADDRESS: 0x0002
NAME
DESCRIPTION
OUI c:r
Organizationally unique identifier.
DEFAULT: 0x4000
ACCESS
RO
BIT(s)
4/5.3.15:0
Table 2-22. XS_DEVICE_IDENTIFIER_2
ADDRESS: 0x0003
DEFAULT: 0x50D0
NAME
DESCRIPTION
OUI c:r
Device identifier. Manufacturer model and revision number
ACCESS
RO
52
Detailed Description
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