TLK3134_1 Datasheet, PDF (133/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
Nine/Ten Bit SERDES Mode - Clock Range Support (RATE[1:0] == 01) (Half)
REFCLK
Jitter SERDES REFCLK SERDES Serial Data Rate (Mbps)
Minimum Maximum Cleaner Minimum Maximum PLL
Half
(MHz) (MHz) Multiplier (MHz) (MHz) Multiplier Minimum Maximum
200.0000 375.0000 OFF 200.0000 375.0000
5
1000.00 1875.00
100.0000 212.5000 OFF 100.0000 212.5000 10
1000.00 2125.00
50.0000 106.2500 OFF 50.0000 106.2500 20
1000.00 2125.00
800.0000 ######## 0.25 200.0000 375.0000
5
1000.00 1875.00
400.0000 850.0000 0.25 100.0000 212.5000 10
1000.00 2125.00
200.0000 375.0000 0.25 50.0000 93.7500
20
1000.00 1875.00
400.0000 750.0000 0.5 200.0000 375.0000
5
1000.00 1875.00
200.0000 375.0000 0.5 100.0000 187.5000 10
1000.00 1875.00
100.0000 212.5000 0.5 50.0000 106.2500 20
1000.00 2125.00
200.0000 375.0000
1
200.0000 375.0000
5
1000.00 1875.00
100.0000 200.0000
1
100.0000 200.0000 10
1000.00 2000.00
50.0000 106.2500
1
50.0000 106.2500 20
1000.00 2125.00
100.0000 187.5000
2
200.0000 375.0000
5
1000.00 1875.00
50.0000 100.0000
2
100.0000 200.0000 10
1000.00 2000.00
25.0000 53.1250
2
50.0000 106.2500 20
1000.00 2125.00
Figure A-8. Reference Clock Selection – 9/10 Bit SERDES Mode – Half Rate (SPEED[1:0] == 01)
Nine/Ten Bit SERDES Mode - Clock Range Support (RATE[1:0] == 10) (Quarter)
REFCLK
Jitter SERDES REFCLK SERDES Serial Data Rate (Mbps)
Minimum Maximum Cleaner Minimum Maximum PLL Quarter
(MHz) (MHz) Multiplier (MHz) (MHz) Multiplier Minimum Maximum
240.0000 375.0000 OFF 240.0000 375.0000
5
600.00 937.50
120.0000 212.5000 OFF 120.0000 212.5000 10
600.00 1062.50
60.0000 106.2500 OFF 60.0000 106.2500 20
600.00 1062.50
800.0000 ######## 0.25 200.0000 375.0000
5
500.00 937.50
400.0000 850.0000 0.25 100.0000 212.5000 10
500.00 1062.50
240.0000 375.0000 0.25 60.0000 93.7500
20
600.00 937.50
400.0000 750.0000 0.5 200.0000 375.0000
5
500.00 937.50
240.0000 375.0000 0.5 120.0000 187.5000 10
600.00 937.50
120.0000 212.5000 0.5 60.0000 106.2500 20
600.00 1062.50
240.0000 375.0000
1
240.0000 375.0000
5
600.00 937.50
120.0000 200.0000
1
120.0000 200.0000 10
600.00 1000.00
60.0000 106.2500
1
60.0000 106.2500 20
600.00 1062.50
120.0000 187.5000
2
240.0000 375.0000
5
600.00 937.50
60.0000 100.0000
2
120.0000 200.0000 10
600.00 1000.00
25.0000 53.1250
2
50.0000 106.2500 20
500.00 1062.50
Figure A-9. Reference Clock Selection –9/10 Bit SERDES Mode – Quarter Rate (SPEED[1:0] == 10)
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APPENDIX A – Frequency Ranges Supported 133