TLK3134_1 Datasheet, PDF (4/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
List of Figures
1-1 System Block Diagram – XAUI.................................................................................................. 14
1-2 System Block Diagram – XAUI Backplane .................................................................................... 15
1-3 Block Diagram – TLK3134 Clocking Architecture............................................................................. 15
2-1 Quad 10-Bit SERDES Application .............................................................................................. 17
2-2 XAUI Mode – XAUI (Serial) Loopback Application ........................................................................... 17
2-3 XAUI Mode - XGMII (Parallel ) Loopback Application........................................................................ 18
2-4 Custom Independent Configuration Application............................................................................... 18
2-5 TLK3134 Block Diagram ......................................................................................................... 19
2-6 Detailed XAUI/1000Base-X Core Block Diagram ............................................................................. 19
2-7 Block Diagram of SERDES Core ............................................................................................... 20
2-8 RGMII – Individual Channel Byte Ordering – Channel 0 Example ......................................................... 23
2-9 RTBI – Individual Channel Byte Ordering – Channel 0 Example........................................................... 24
2-10 TBI – Individual Channel Byte Ordering – Channel 0 Example............................................................. 25
2-11 GMII – Individual Channel Byte Ordering – Channel 0 Example ........................................................... 26
2-12 EBI – Individual Channel Byte Ordering – Channel 0 Example............................................................. 27
2-13 REBI – Individual Channel Byte Ordering – Channel 0 Example........................................................... 28
2-14 NBI – Individual Channel Byte Ordering – Channel 0 Example ............................................................ 29
2-15 RNBI – Individual Channel Byte Ordering – Channel 0 Example .......................................................... 30
2-16 TBID – Individual Channel Byte Ordering – Channel 0 Example........................................................... 31
2-17 NBID – Individual Channel Byte Ordering – Channel 0 Example .......................................................... 32
2-18 Receive Interface Timing – Source Centered/Aligned ....................................................................... 33
2-19 Transmit Interface Timing ........................................................................................................ 34
2-20 Transmission Latency ............................................................................................................ 35
2-21 Receiver Latency.................................................................................................................. 35
2-22 Channel Synchronization State Machine ...................................................................................... 38
2-23 End of Packet Error Detection................................................................................................... 39
2-24 Column De-Skew State Machine ............................................................................................... 40
2-25 Channel Deskew Using Alignment Code ...................................................................................... 42
2-26 Inter-Packet Gap Management.................................................................................................. 43
2-27 IPG Management State Machine ............................................................................................... 44
2-28 Clock Tolerance Compensation: Add .......................................................................................... 45
2-29 Clock Tolerance Compensation: Drop ......................................................................................... 46
2-30 Example High Speed I/O AC Coupled Mode.................................................................................. 47
2-31 Output differential voltage with 1-tap FIR de-emphasis...................................................................... 47
2-32 CL45 - Management Interface Extended Space Address Timing .......................................................... 49
2-33 CL45 – Management Interface Extended Space Write Timing ............................................................. 49
2-34 CL45 – Management Interface Extended Space Read Timing ............................................................. 49
2-35 CL45 – Management Interface Extended Space Read And Increment Timing........................................... 50
2-36 CL22 – Management Interface Read Timing.................................................................................. 50
4
List of Figures
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