TLK3134_1 Datasheet, PDF (89/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
BIT(s)
4/5.38145.7:0
Table 2-164. CH1_TESTFAIL_ERR_COUNTER
ADDRESS: 0x9501
NAME
Ch1_Testfail error
counter[7:0]
DEFAULT: 0x00FD
DESCRIPTION
This counter reflects error count during PRBS test. Counter increments
for each received character that has an error. Counter clears upon read.
When ST = 0, counter value is valid when PRBS_EN pin is set or when
SERDES RX test pattern registers bits are set
When ST = 1, counter value is valid only when SERDES RX test pattern
verification bits are set
ACCESS
COR
BIT(s)
4/5.38146.7:0
Table 2-165. CH2_TESTFAIL_ERR_COUNTER
ADDRESS: 0x9502
NAME
Ch2_Testfail error counter
DEFAULT: 0x00FD
DESCRIPTION
This counter reflects error count during PRBS test. Counter increments
for each received character that has an error. Counter clears upon read.
When ST = 0, counter value is valid when PRBS_EN pin is set or when
SERDES RX test pattern registers bits are set
When ST = 1, counter value is valid only when SERDES RX test pattern
verification bits are set
ACCESS
COR
BIT(s)
4/5.38147.7:0
Table 2-166. CH3_TESTFAIL_ERR_COUNTER
ADDRESS: 0x9503
NAME
Ch3_Testfail error counter
DEFAULT: 0x00FD
DESCRIPTION
This counter reflects error count during PRBS test. Counter increments
for each received character that has an error. Counter clears upon read.
When ST = 0, counter value is valid when PRBS_EN pin is set or when
SERDES RX test pattern registers bits are set
When ST = 1, counter value is valid only when SERDES RX test pattern
verification bits are set
ACCESS
COR
Table 2-167. STCI_CONTROL_STATUS
ADDRESS: 0x9600
BIT(s)
NAME
4/5.38400.15 STCI_CLK
4/5.38400.11:10 STCI_CFG[1:0]
4/5.38400.7 STCI_D
4/5.38400.3 STCI_Q
DEFAULT: 0x0000
DESCRIPTION
Bit to generate STCI clock in functional mode.
STCI CFG control
STCI data in
STCI read data
ACCESS
RW
RO
BIT(s)
4/5.38401.15
ADDRESS: 0x9601
NAME
TESTCLKT
Table 2-168. TESTCLK_CONTROL
DEFAULT: 0x0000
DESCRIPTION
Bit to generate TESTCLKT clock in functional mode.
For TI test purposes only
ACCESS
RW
BIT(s)
4/5.38656.15
Table 2-169. BIDI_CMOS_CONTROL
ADDRESS: 0x9700
NAME
MDIO Disable Comp Test
Control
DEFAULT: 0x0000
DESCRIPTION
0 = MDIO/MDC Bidi cells automatically detects operating voltage (Default)
1 = MDIO/MDC Bidi cells expects 2.5 V operating voltage
ACCESS
RW
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