TLK3134_1 Datasheet, PDF (16/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
www.ti.com
2 Detailed Description
2.1 Clocking Modes
The TLK3134 contains an internal low-bandwidth, low-jitter high quality LC oscillator that may be
configured as a jitter cleaner. The jitter cleaner oscillator has a high frequency narrow band of operation
that may be used to generate all common reference clock frequencies by way of programmable pre-scaler
and post-scaler registers. In this manner a poor quality input reference clock can be input to the jitter
cleaner which will lock to the reference clock and provide a clean reference to the internal SERDES PLLs.
Appendix A defines in detail the clocking possibilities, and device settings.
Alternatively, the jitter cleaner may be used to lock to a recovered byte clock from RX channel 0 and
remove jitter that may have transferred through the clock/data recovery circuit from the serial data stream
to the recovered byte clock (including parallel output data timing). In this way the recovered byte clock
may be extracted from the serial data stream yet be suitable for use in applications that require a clean
clock source derived from the serial data stream. The TLK3134 jitter cleaner may only be used on the
recovered byte clock from Channel 0. If the jitter cleaner is used to clean the recovered byte clock, it may
not be used to clean the input reference clock, and the PLL at the center of the deserializer core must
have a clean low-jitter reference clock from an external clock source, preferably a low-jitter crystal based
oscillator. Note that the Transmit SERDES macro can run from the cleaned recovered RX channel 0 byte
clock which allows for the outgoing TX serial data rate for all channels to exactly match the incoming data
rate of RX Channel 0.
The TLK3134 clocking architecture allows for bypass of the Jitter cleaner PLL in cases where power or
application board area is critical.
See Figure 1-3 Clocking Architecture for a representation of the use of the jitter cleaner in the TLK3134.
2.2 Operating Frequency Range
The TLK3134 is optimized for operation at a serial data rate of 600 Mbit/s through 3.75 Gbit/s. The
external differential (optionally single-ended) reference clock has a large operating frequency range
allowing support for many different applications. The reference clock frequency must be within ±200 PPM
of the incoming serial data rate, and have less than 40ps of jitter. Table 2-1 shows a summary of
frequency ranges supported. For more details, see Appendix A. In all applications except XAUI/10GFC,
the transmit parallel clock must be frequency locked (0 ppm) to the supplied REFCLK frequency
(XAUI/10GFC allows ±200 ppm).
Table 2-1. Supported Protocol Rates and REFCLK Values
PROTOCOL
XAUI – 10G Ethernet
10 Gigabit Fibre Channel
1G Ethernet
1X/2X Fibre Channel
OBSAI
CPRI
Generic TBI
Generic RTBI
Generic NBID/TBID
Refclk (MHz)
78.125/156.25/312.5
79.6875/159.375/ 318.75
62.5/125/250
53.125/106.25/212.5
76.8/153.6/307.2
61.44/122.88/245.76
50 → 375 MHz
50 → 375 MHz
50 → 375 MHz
LINE RATE (Gbps)
3.125
3.1875
1.25
2.125
1.0625
3.072
1.536
0.768
2.4576
1.2288
0.6144
0.600 → 3.75
0.600 → 1.6
0.600 → 3.2
16
Detailed Description
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