TLK3134_1 Datasheet, PDF (119/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
TIMING
MODE
NAME
NBI
RNBI
TBID
NBID
Table 4-2. Parallel Interface – Valid Signal Operational Mode Definitions (continued)
USAGE MODE
Nine Bit Interface Mode (NBI)
(Un-encoded Data Byte + 1 Control Bit)
SDR Timing Support
See Section 4.12: HSTL Output Switching Characteristics (SDR Timing
Mode Only) and Section 4.14: HSTL (SDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In NBI Mode
CH0: TX Control Bit = TXC_[0]
CH1: TX Control Bit = TXC_[1]
CH2: TX Control Bit = TXC_[2]
CH3: TX Control Bit = TXC_[3]
CH0: RX Control Bit = RXC_[0]
CH1: RX Control Bit = RXC_[1]
CH2: RX Control Bit = RXC_[2]
CH3: RX Control Bit = RXC_[3]
Reduced Nine Bit Interface Mode (RNBI)
(Un-encoded Data Byte + 1 Control Bit)
DDR Timing Support
See Section 4.11: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.13: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In RNBI Mode
CH0: TX Control Bit = TXD_[4]
CH1: TX Control Bit = TXD_[12]
CH2: TX Control Bit = TXD_[20]
CH3: TX Control Bit = TXD_[28]
CH0: RX Control Bit = RXD_[4]
CH1: RX Control Bit = RXD_[12]
CH2: RX Control Bit = RXD_[20]
CH3: RX Control Bit = RXD_[28]
Ten Bit Interface DDR Mode (TBID)
Only DDR Timing Supported
See Section 4.11: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.13: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In TBID Mode
CH0: TX Data Bit 8 = TXC_[0]
CH1: TX Data Bit 8 = TXC_[1]
CH2: TX Data Bit 8 = TXC_[2]
CH3: TX Data Bit 8 = TXC_[3]
CH0: TX Data Bit 9 = TXC_[4]
CH1: TX Data Bit 9 = TXC_[5]
CH2: TX Data Bit 9 = TXC_[6]
CH3: TX Data Bit 9 = TXC_[7]
CH0: RX Data Bit 8 = RXC_[0]
CH1: RX Data Bit 8 = RXC_[1]
CH2: RX Data Bit 8 = RXC_[2]
CH3: RX Data Bit 8 = RXC_[3]
CH0: RX Data Bit 9 = RXC_[4]
CH1: RX Data Bit 9 = RXC_[5]
CH2: RX Data Bit 9 = RXC_[6]
CH3: RX Data Bit 9 = RXC_[7]
Nine Bit Interface DDR Mode (NBID)
(Un-encoded Data Byte + 1 Control Bit)
DDR Timing Support
See Section 4.11: HSTL Output Switching Characteristics (DDR Timing
Mode Only) and Section 4.13: HSTL (DDR Timing Mode Only) Input Timing
Requirements for AC timing details.
Note: In NBID Mode
CH0: TX Control Bit = TXC_[0]
CH1: TX Control Bit = TXC_[1]
CH2: TX Control Bit = TXC_[2]
CH3: TX Control Bit = TXC_[3]
CH0: RX Control Bit = RXC_[0]
CH1: RX Control Bit = RXC_[1]
CH2: RX Control Bit = RXC_[2]
CH3: RX Control Bit = RXC_[3]
TX SIGNALS USED
TXDATA = TXC_ [0], TXD[7:0]
TXCLK = TXCLK_ [0]
-or-
TXDATA = TXC_ [1],
TXD_ [15:8]
TXCLK = TXCLK_ [1]
-or-
TXDATA = TXC_ [2],
TXD_ [23:16]
TXCLK = TXCLK_ [2]
-or-
TXDATA = TXC_ [3],
TXD_ [31:24]
TXCLK = TXCLK_ [3]
TXDATA = TXD_[4:0]
TXCLK = TXCLK_[0]
-or-
TXDATA = TXD_[12:8]
TXCLK = TXCLK_ [1]
-or-
TXDATA = TXD_ [20:16]
TXCLK = TXCLK_ [2]
-or-
TXDATA = TXD_ [28:24]
TXCLK = TXCLK_ [3]
TXDATA = TXC_ [4],TXC_ [0],
TXD[7:0]
TXCLK = TXCLK_ [0]
-or-
TXDATA = TXC_ [5],TXC_ [1],
TXD_ [15:8] TXCLK = TXCLK_ [1]
-or-
TXDATA = TXC_ [6],TXC_ [2],
TXD_ [23:16]
TXCLK = TXCLK_ [2]
-or-
TXDATA = TXC_ [7],TXC_ [3],
TXD_ [31:24]
TXCLK = TXCLK_ [3]
TXDATA = TXC_ [0], TXD[7:0]
TXCLK = TXCLK_ [0]
-or-
TXDATA = TXC_ [1], TXD_ [15:8]
TXCLK = TXCLK_ [1]
-or-
TXDATA = TXC_ [2], TXD_ [23:16]
TXCLK = TXCLK_ [2]
-or-
TXDATA = TXC_ [3], TXD_ [31:24]
TXCLK = TXCLK_ [3]
RX SIGNALS USED
RXDATA = RXC_ [0], RXD[7:0]
RXCLK = RXCLK_ [0]
-or-
RXDATA = RXC_ [1],
RXD_ [15:8]
RXCLK = RXCLK_ [1]
-or-
RXDATA = RXC_ [2],
RXD_ [23:16]
RXCLK = RXCLK_ [2]
-or-
RXDATA = RXC_ [3],
RXD_ [31:24]
RXCLK = RXCLK_ [3]
RXDATA = RXD_[4:0]
RXCLK = RXCLK_[0]
-or-
RXDATA = RXD_ [12:8]
RXCLK = RXCLK_ [1]
-or-
RXDATA = RXD_ [20:16]
RXCLK = RXCLK_ [2]
-or-
RXDATA = RXD_ [28:24]
RXCLK = RXCLK_ [3]
RXDATA = RXC_ [4],RXC_ [0],
RXD[7:0]
RXCLK = RXCLK_ [0]
-or-
RXDATA = RXC_ [5],RXC_ [1],
RXD_ [15:8]
RXCLK = RXCLK_ [1]
-or-
RXDATA = RXC_ [6],RXC_ [2],
RXD_ [23:16]
RXCLK = RXCLK_ [2]
-or-
RXDATA = RXC_ [7],RXC_ [3],
RXD_ [31:24]
RXCLK = RXCLK_ [3]
RXDATA = RXC_ [0], RXD[7:0]
RXCLK = RXCLK_ [0]
-or-
RXDATA = RXC_ [1], RXD_ [15:8]
RXCLK = RXCLK_ [1]
-or-
RXDATA = RXC_ [2], RXD_ [23:16]
RXCLK = RXCLK_ [2]
-or-
RXDATA = RXC_ [3], RXD_ [31:24]
RXCLK = RXCLK_ [3]
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