TLK3134_1 Datasheet, PDF (63/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
2.9 1G Programmers Reference
Following registers can be addressed directly only through Clause 22 (1G Related Registers). Clause 22
access is valid only when “ST” pin is set to 1. These bits are per channel basis. Channel identification is
based on PHY (Port) address field.
Channel 0 can be accessed by setting 2 LSB’s of PHY address to 00.
Channel 1 can be accessed by setting 2 LSB’s of PHY address to 01.
Channel 2 can be accessed by setting 2 LSB’s of PHY address to 10.
Channel 3 can be accessed by setting 2 LSB’s of PHY address to 11.
Registers 30 (5’h1E) and 31 (5’h1F) are global in 1G mode. These registers contents are same when
accessed through any of the 4 channels mentioned above.
Table 2-74. PHY_CONTROL_1
BIT(s)
0. 15
0. 14
0. 13
0. 12
0. 11
0. 10
0. 9
0. 8
0. 7
0. 6
Reset
ADDRESS: 0x00
NAME
Loopback
Speed Selection(LSB)
Auto-Negotiation Enable
Power Down
Isolate
Restart Auto-Negotiation
Duplex Mode
Collision Test
Speed Selection (MSB)
DEFAULT: 0x0140
DESCRIPTION
1 = PHY reset (including all registers and both Tx/Rx datapaths)
0 = Normal operation (Default 1’b0)
Logically OR’ed with PLOOP
1 = Enable loop back mode. In this mode, serial output of the channel is
looped back onto serial input.
0 = Disable loop back mode (Default 1’b0)
This is the least significant bit of the speed selection bits (MSB is 0.6).
{0.6,0.13} = 2’b10 1000Base-X Rate
This bit always reads 0.
Always reads 0. (Auto-Negotiation not supported)
Setting this bit high powers down respective channel, with exception that
MDIO interface stays active. Serdes PLL’s can be shut down by
de-asserting bits 36864.12 and 36864.4. Jitter cleaner PLL can be shut
down by de-asserting 37127.15
1 = Power Down mode is enabled.
0 = Normal operation (Default 1’b0)
Setting this bit high isolates the channel from the parallel interface.
Inputs are ignored; Outputs are set to high impedance.
1 = Isolate is enabled
0 = Normal operation (Default 1’b0)
Always reads 0. (Auto-Negotiation not supported)
Always reads 1. (Only Full duplex supported)
Not Applicable. Read will return a 0.
This is the most significant bit of the speed selection bits (LSB is 0.13).
{0.6,0.13} = 2’b10 1000Base-X Rate
This bit always reads 1
(1) After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.
ACCESS
RW SC⁽¹⁾
RW
RO
RO
RW
RW
RO
RO
RO
RO
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