TLK3134_1 Datasheet, PDF (66/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
BIT(s)
17.11
17.10
17.9
17.8
17.7
17.6
17.5
17.4
17.3
17.2
17.1
17.0
Table 2-80. PHY_CH_CONTROL_2 (continued)
ADDRESS: 0x11
NAME
LOS Override
CTC enable
Full DDR mode
RCLK out enable
Comma enable
FC enable
Data mode
Nibble order
PCS TX_RX Enable
Encode Decode Enable
TX Edge Mode
RX Edge Mode
DEFAULT: 0x3590
DESCRIPTION
1 = Overrides Loss of signal (LOS) status coming from SERDES.
Synchronization turned on irrespective of LOS status
0 = Synchronization depends on LOS status. (Default 1’b0)
1 = Clock Tolerance Compensation on receive datapath is enabled
(Default 1’b1)
0 = Clock Tolerance Compensation on receive datapath is disabled
1 = Sets the device in full DDR mode (NBID/TBID modes)
0 = Disables full DDR mode (Default)
1 = Enables RX_CLK out (Default 1’b1)
0 = Disables RX_CLK out.
RX_CLK will be low when this bit is de-asserted
1 = Enables comma detection (Default 1’b1)
0 = Disables comma detection
1 = Enables FC_PH overlay detection. This is needed in 1x/2x Fiber
channel mode to allow proper detection of EOF 8B/10B disparity
0 = Disables FC_PH overlay detection (Default 1’b0)
Valid only when 17.9 (Full DDR mode) is LOW.
1 = Enables DDR data mode on parallel Transmit and Receive directions
(data clocked on both rising and falling edge)
0 = Enables SDR data mode on parallel Transmit and Receive directions
(data is clocked only on rising edge or only on falling edge) (Default 1’b0)
Applicable only in non FULL DDR modes
1 = LSB on rising edge followed by MSB on falling edge (Default 1’b1)
0 = MSB on rising edge followed by LSB on falling edge
1 = Enables 1000Base-X PCS Tx & PCS Rx functions
0 = Disables 1000Base-X PCS Tx Function (Default 1’b0)
0 = 8B/10B encode decode functions are disabled (Default 1’b0)
1 = 8B/10B encode decode functions are enabled
When channel is in DDR mode
1 = Source aligned timing on transmit parallel interface.
0 = Source centered timing on transmit parallel interface. Data is latched
on both rising and falling clock edges.
When channel is in SDR mode
1 = Rising edge align mode. Incoming parallel data is aligned to rising
edge of parallel input clock. Internally data is latched at the falling edge
of the clock.
0 = Falling edge align mode. Incoming data is aligned to falling edge of
parallel input clock. Internally data is latched at the rising edge of the
clock
When channel is in DDR mode
1 = Source aligned timing on receive parallel interface. Data changes at
clock edge.
0 = Source centered timing on receive parallel interface.
When channel is in SDR mode
1 = Rising edge align mode. Outgoing parallel data is aligned to the
rising edge of the parallel output clock
0 = Falling edge align mode. Outgoing parallel data is aligned to the
falling edge of the parallel output clock
BIT(s)
18.15
18.14
18.13
Table 2-81. PHY_RX_CTC_FIFO_STATUS
ADDRESS: 0x12
NAME
RX_CTC_Reset
RX_CTC_Insert
RX_CTC_Delete
DEFAULT: 0x0000
DESCRIPTION
When high indicates overflow or underflow has occurred in CTC FIFO
and FIFO has been reset.
When high indicates RX CTC has inserted at least one ordered set.
When high indicates RX CTC has deleted at least one ordered set.
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ACCESS
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RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
ACCESS
RO/LH
66
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