TLK3134_1 Datasheet, PDF (69/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

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TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
Table 2-93. SERDES_PLL_CONFIG⁽¹⁾
ADDRESS: 0x9000
DEFAULT: 0x1515
BIT(s)
NAME
DESCRIPTION
4/5.36864.14:13
Loop Bandwidth
RX(LB_RX)
SERDES RX PLL Bandwidth settings
00 = Applicable when JC PLL is not engaged
01 = Reserved
10 = Reserved
11 = Applicable when JC PLL is engaged
4/5.36864. 12 ENPLL_RX
0 = Disables PLL in SERDES RX
1 = Enable PLL in SERDES RX
4/5.36864.11:8
PLL Multiplier factor SERDES RX PLL multiplier setting
RX (MPY_RX)
See Table 94: PLL Multiplier Control
4/5.36864.7
BUSWIDTH
1 = 8 bit mode. Applicable for only EBI and REBI modes
0 = 10 Bit mode. Applicable for all other modes
4/5.36864.6:5
Loop Bandwidth TX
(LB_TX)
SERDES TX PLL Bandwidth settings
00 = Applicable when JC PLL is not engaged
01 = Reserved
10 = Reserved
11 = Applicable when JC PLL is engaged
4/5.36864.4
ENPLL_TX
0 = Disables PLL in SERDES TX
1 = Enable PLL in SERDES TX
4/5.36864. 3:0
PLL Multiplier factor SERDES TX PLL multiplier setting
TX (MPY_TX)
See Table 94: PLL Multiplier Control
(1) These are global PLL control bits and will be applicable to all 4 channels.
ACCESS
RW
RW
RW
RW
RW
RW
RW
Table 2-94. PLL Multiplier Control
36864[11:8]/ 36864[3:0]
VALUE
PLL MULTIPLIER
FACTOR
0000
4x
0001
5x
0010
6x
0011
Reserved
0100
8x
0101
10x
0110
12x
0111
12.5x
36864[11:8]/ 36864[3:0]
VALUE
PLL MULTIPLIER
FACTOR
1000
15x
1001
20x
1010
25x
1011
Reserved
1100
Reserved
1101
50x
1110
60x
1111
Reserved
Table 2-95. SERDES_RATE_CONFIG_TX_RX⁽¹⁾
BIT(s)
4/5.36865.15:14
4/5.36865.13:12
4/5.36865.11:10
ADDRESS: 0x9001
DEFAULT: 0x0000
NAME
DESCRIPTION
RATE_0_TX
TX Ch 0 Operating rate
00 = Full rate (2 data samples/output per PLL output clock cycle)
01 = Half rate (1 data sample/output per PLL output clock cycle)
10 = Quarter rate (1 data sample/output per 2 PLL output clock cycle)
11 = Reserved
RATE _1_TX
TX Ch 1 Operating rate
00 = Full rate (2 data samples/output per PLL output clock cycle)
01 = Half rate (1 data sample/output per PLL output clock cycle)
10 = Quarter rate (1 data sample/output per 2 PLL output clock cycle)
11 = Reserved
RATE _2_TX
TX Ch 2 Operating rate
00 = Full rate (2 data samples/output per PLL output clock cycle)
01 = Half rate (1 data sample/output per PLL output clock cycle)
10 = Quarter rate (1 data sample/output per 2 PLL output clock cycle)
11 = Reserved
ACCESS
RW
RW
RW
(1) These are global PLL control bits and will be applicable to all 4 channels.
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Detailed Description
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