TLK3134_1 Datasheet, PDF (46/150 Pages) Texas Instruments – 4-Channel Multi-Rate Transceiver

TLK3134
4-Channel Multi-Rate Transceiver
SLLS838D – MAY 2007 – REVISED JULY 2008
Packet
www.ti.com
IPG
Input
RDP/N0 K R S D D D D ... D D D D A R R K S D
RDP/N1 K R D D D D D ... D D D T A R R K D D
RDP/N2 ^{K R D D D D D ... D D D K A R R K D D}
RDP/N3 K R D D D D D ... D D D K A R R K D D
RXD(7:0)
Dropped Column
I I S D D D D ... D D D D I I I S D D
Output
RXD(15:8)
RXD(23:16)
I I D D D D D ... D D D T I I I D D D
I I D D D D D ... D D D I I I I D D D
RXD(31:24) I I D D D D D ... D D D I I I I D D D
S = Start of Packet, D = Data, T = End of Packet, A = K28.3,
K = K28.5, R = K28.0, I = Idle
Figure 2-29. Clock Tolerance Compensation: Drop
2.7.27 Parallel to Serial
The parallel-to-serial shift register on each channel takes in data and converts it to a serial stream. The
shift register is clocked by the internally generated bit clock, which is 10 times the reference clock
(REFCLKP/REFCLKN) frequency. The least significant bit (LSB) for each channel is transmitted first.
2.7.28 Serial to Parallel
For each channel, serial data is received on the RDPx/RDNx pins. The interpolator and clock recovery
circuit will lock to the data stream if the clock to be recovered is within ±200 PPM of the internally
generated bit rate clock. The recovered clock is used to retime the input data stream. The serial data is
then clocked into the serial-to-parallel shift registers. If enabled, the 10-bit wide parallel data is then fed
into 8b/10b decoders.
2.7.29 High Speed CML Output
The high speed data output driver is implemented using Current Mode Logic (CML) with integrated pull up
resistors requires no external components. The line can be directly coupled or AC coupled. Under many
circumstances, AC coupling is desirable.
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Detailed Description
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