UPSD3422_06 Datasheet, PDF (88/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

Standard 8032 timer/counters
uPSD34xx
period (12 / f_OSC, seconds). However, if MCU_CLK is divided by the SFR CCON0, then the
sample period must be calculated based on the resultant, longer, MCU_CLK frequency. In
this case, an external clock signal on pins C0, C1, or T2 should have a duration longer than
one MCU machine cycle, t_{MACH_CYC}. Section 19.5: Watchdog timer, WDT on page 84
explains how to estimate t_{MACH_CYC}.
Table 41. TCON: Timer control register (SFR 88h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit
Symbol
R/W
Definition
Timer 1 overflow interrupt flag. Set by hardware upon overflow.
7
TF1
R
Automatically cleared by hardware after firmware services the
interrupt for Timer 1.
6
TR1
R,W
Timer 1 run control. 1 = Timer/Counter 1 is on, 0 =
Timer/Counter 1 is off.
Timer 0 overflow interrupt flag. Set by hardware upon overflow.
5
TF0
R
Automatically cleared by hardware after firmware services the
interrupt for Timer 0.
4
TR0
R,W
Timer 0 run control. 1 = Timer/Counter 0 is on, 0 =
Timer/Counter 0 is off.
Interrupt flag for external interrupt pin, EXTINT1. Set by
3
IE1
R
hardware when edge is detected on pin. Automatically cleared
by hardware after firmware services EXTINT1 interrupt.
2
IT1
R,W
Trigger type for external interrupt pin EXTINT1. 1 = falling
edge, 0 = low-level
Interrupt flag for external interrupt pin, EXTINT0. Set by
1
IE0
R
hardware when edge is detected on pin. Automatically cleared
by hardware after firmware services EXTINT0 interrupt.
0
IT0
R,W
Trigger type for external interrupt pin EXTINT0. 1 = falling
edge, 0 = low-level
20.3
SFR, TCON
Timer 0 and Timer 1 share the SFR, TCON, that controls these timers and provides
information about them. See Table 41 on page 88.
Bits IE0 and IE1 are not related to Timer/Counter functions, but they are set by hardware
when a signal is active on one of the two external interrupt pins, EXTINT0 and EXTINT1. For
system information on all of these interrupts, see Table 16 on page 53, Interrupt Summary.
Bits IT0 and IT1 are not related to Timer/Counter functions, but they control whether or not
the two external interrupt input pins, EXTINT0 and EXTINT1 are edge or level triggered.
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