UPSD3422_06 Datasheet, PDF (149/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
USB interface
Figure 53. Control transfer
SETUP ADDR ENDP CRC5
Token Packet
Data0
Payload _CRC16
Data (8 bytes)
Data Packet
ACK
Handshake Packet
SETUP
Stage
IN ADDR ENDP CRC5
Token Packet
Data1
Payload
Data
Data Packet
CRC16
ACK
Handshake Packet
DATA
Stage
(Optional)
OUT ADDR ENDP CRC5
Token Packet
Data1 CRC16
Data Packet
ACK
Handshake
Packet
STATUS
Stage
AI10492
25.3
25.3.1
25.3.2
Endpoint FIFOs
The uPSD34xx’s USB module includes 5 endpoints and 10 FIFOs. Each endpoint has two
FIFOs with one for IN and the other for OUT transactions. Each FIFO is 64 bytes long and
is selectively made visible in a 64-byte XDATA segment for CPU access. For efficient data
transfers, the FIFOs may be paired for double buffering. With double buffering, the CPU may
operate on the contents in one buffer while the SIE is transmitting or receiving data in the
paired buffer. uPSD34xx supported endpoints and FIFOs are shown in Table 68
Busy Bit (BSY) operation
Each FIFO has a busy bit (BSY) that indicates when the USB SIE has ownership of the
FIFO. When the SIE has ownership of the FIFO, it is either writing data to or reading data
from the FIFO. The SIE writes data to the FIFO when it is receiving an OUT packet and
reads data from the FIFO when it is sending data in response to an IN packet. The CPU is
only permitted to access the FIFO when it is not busy and accesses to it while busy are
ignored. Once the IN FIFO has been written with data by the CPU, the CPU updates the
USIZE register with the number of bytes written to the FIFO. The value written to the USIZE
register tells the SIE the number of bytes to send to the host in response to an IN packet.
Once the USIZE register is written, the FIFOs busy bit is set and remains set until the data
has been transmitted in response to an IN packet. The busy bit for an OUT FIFO is set as
soon as the SIE starts receiving an OUT packet from the host. Once all the data has been
received and written to the FIFO, the SIE clears the busy bit and writes the number of bytes
received to the USIZE register.
Busy bit and interrupts
When the FIFO’s interrupt is enabled, a transition of the busy bit from a '1' to a '0' (when
ownership of the FIFO changes from the SIE to the CPU) generates a USB interrupt with the
corresponding flag set. For an interrupt on an IN FIFO, the CPU must fill the FIFO with the
next set of data to be sent and then update the USIZE register with the number of bytes to
send. For an interrupt on an OUT FIFO, the CPU reads the USIZE register to determine the
number of bytes received and then reads that number of data bytes out of the FIFO.
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