UPSD3422_06 Datasheet, PDF (276/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

DC and AC parameters
uPSD34xx
Table 170. CPLD macrocell asynchronous clock mode timing (3V PSD module)
Symbol
Parameter
Conditions
Min
Max
PT ^{Turbo Slew}
Aloc _{Off Rate}
Unit
Maximum Frequency
External Feedback
1/(t_SA+t_COA)
f_MAXA
Maximum Frequency
Internal Feedback
(f_CNTA)
Maximum Frequency
Pipelined Data
1/(t_SA+t_COA–
10)
1/(t_CHA+t_CLA)
t_SA
t_HA
t_CHA
t_CLA
t_COA
t_ARD
t_MINA
Input Setup Time
10
Input Hold Time
12
Clock High Time
17
Clock Low Time
13
Clock to Output Delay
CPLD Array Delay
Any macrocell
Minimum Clock Period
1/f_CNTA
36
21.7
27.8
33.3
+ 4 + 15
+ 15
+ 15
31
+ 15 – 6
20 + 4
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
Figure 105. Input macrocell timing (product term clock)
t_INH
t_INL
PT CLOCK
t_IS
t_IH
INPUT
OUTPUT
AI03101
t_INO
Table 171. Input macrocell timing (5V PSD module)
Symbol
Parameter
Condition
s
Min
Max
PT
Aloc
Turbo
Off
Unit
t_IS Input Setup Time
t_IH Input Hold Time
t_INH NIB Input High Time
t_INL NIB Input Low Time
t_INO
NIB Input to Combinatorial
Delay
(Note 1)
0
(Note 1) 15
(Note 1)
9
(Note 1)
9
ns
+ 10 ns
ns
ns
(Note 1)
34
+ 2 + 10 ns
Note: 1 Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch
timings refer to t_AVLX and t_LXAX.
276/293