UPSD3422_06 Datasheet, PDF (197/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
PSD module
28.2.7
Note:
The VM register
One of the csiop registers (the VM Register) controls whether or not the 8032 bus control
signals RD, WR, and PSEN are routed to the Main Flash memory, or the Secondary Flash
memory. Routing of these signals to these PSM Module memories determines if memories
reside in 8032 program address space, 8032 XDATA space, or both. The initial setting of the
VM Register is determined by a choice in PSDsoft Express and programmed into the
uPSD34xx in a non-volatile fashion using JTAG. This initial setting is loaded into the VM
Register upon power-up and also loaded upon any reset event. However, the 8032 may
override the initial VM Register setting at run-time by writing to the VM Register, which is
useful for IAP.
Table 104 on page 197 defines bit functions within the VM Register.
Bit 7, PIO_EN, is not related to the memory manipulation functions of Bits 1, 2, 3, and 4.
SRAM and csiop registers are always in XDATA space and cannot reside in program space.
Figure 70 on page 198 illustrates how the VM Register affects the routing of RD, WR, and
PSEN to the memories on the PSD Module. As an example, if we apply the value 0Ch to the
VM Register to implement the memory map example shown in Figure 64 on page 192, then
the routing of RD, WR, and PSEN would look like that shown in Figure 71 on page 198.
In this example, the configuration is specified in PSDsoft Express and programmed into the
uPSD34xx using JTAG. Upon power-on or any reset condition, the non-volatile value 0Ch is
loaded into the VM Register. At runtime, the value 0Ch in the VM Register may be changed
(overridden) by the 8032 if desired to implement IAP or other functions.
Table 104. VM register (address = csiop + offset E2h)
Bit 7
PIO_EN
Bit 6
Bit 5
Bit 4
Main Flash
XDATA
Space
Bit 3
Secondary
Flash
XDATA
Space
Bit 2
Main Flash
Program
Space
Bit 1
Secondary
Flash
Program
Space
Bit 0
0 = disable
Peripheral
I/O Mode on
Port A
not
used
1 = enable
Peripheral
I/O Mode on
Port A
not
used
not
used
not
used
0 = RD or
WR cannot
access
Main Flash
0 = RD or
WR cannot
access
Secondary
Flash
0 = PSEN
cannot
access
Main Flash
0 = PSEN
cannot
access
Secondary
Flash
1 = RD or
WR can
access
Main Flash
1 = RD or
WR can
access
Secondary
Flash
1 = PSEN
can access
Main Flash
1 = PSEN
can access
Secondary
Flash
not used
not used
Note: 1 Default value of Bits 1, 2, 3, and 4 is loaded from Non-Volatile setting as specified from
PSDsoft Express upon any reset or power-up condition. The default value of these bits can
be overridden by 8032 at run-time.
2 Default value of Bit 7 is zero upon any reset condition.
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