UPSD3422_06 Datasheet, PDF (85/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
Supervisory functions
To prevent the WDT from timing out and generating a reset, firmware must repeatedly write
some value to WDRST before the count reaches FFFFFh. Whenever WDRST is written, the
upper 8 bits of the 24-bit counter are loaded with the written value, and the lower 16 bits of
the counter are cleared to 0000h.
The WDT time-out period can be adjusted by writing a value other that 00h to WDRST. For
example, if WDRST is written with 04h, then the WDT will start counting 040000h, 040001h,
040002h, and so on for each MCU machine cycle. In this example, the WDT time-out period
is shorter than if WDRST was written with 00h, because the WDT is an up-counter. A value
for WDRST should never be written that results in a WDT time-out period shorter than the
time required to complete the longest code task in the application, else unwanted WDT
overflows will occur.
Figure 24. Watchdog counter
23
15
8-bits
8-bits
7
0
8-bits
SFR, WDRST
AI09604
The formula to determine WDT time-out period is:
WDT_PERIOD = t_{MACH_CYC} x N_OVERFLOW
N_OVERFLOW is the number of WDT up-counts required to reach FFFFFFh. This is
determined by the value written to the SFR, WDRST.
t_{MACH_CYC} is the average duration of one MCU machine cycle. By default, an MCU machine
cycle is always 4 MCU_CLK periods for uPSD34xx, but the following factors can sometimes
add more MCU_CLK periods per machine cycle:
● The number of MCU_CLK periods assigned to MCU memory bus cycles as determined
in the SFR, BUSCON. If this setting is greater than 4, then machine cycles have
additional MCU_CLK periods during memory transfers.
● Whether or not the PFQ/BC circuitry issues a stall during a particular MCU machine
cycle. A stall adds more MCU_CLK periods to a machine cycle until the stall is
removed.
t_{MACH_CYC} is also affected by the absolute time of a single MCU_CLK period. This number
is fixed by the following factors:
● Frequency of the external crystal, resonator, or oscillator: (f_OSC)
● Bit settings in the SFR CCON0, which can divide f_OSC and change MCU_CLK
As an example, assume the following:
1. f_OSC is 40MHz, thus its period is 25ns.
2. CCON0 is 10h, meaning no clock division, so the period of MCU_CLK is also 25ns.
3. BUSCON is C1h, meaning the PFQ and BC are enabled, and each MCU memory bus
cycle is 4 MCU_CLK periods, adding no additional MCU_CLK periods to MCU machine
cycles during memory transfers.
4. Assume there are no stalls from the PFQ/BC. In reality, there are occational stalls but
their occurance has minimal impact on WDT timeout period.
5. WDRST contains 00h, meaning a full 2²⁴ up-counts are required to reach FFFFFh and
generate a reset.
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