UPSD3422_06 Datasheet, PDF (138/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

SPI (synchronous peripheral interface)
uPSD34xx
Figure 48. SPI interface, master mode only
INTR
to
8032
8032 MCU DATA BUS
8
8
SPICON0, SPICON1
- CONTROL REGISTERS
SPITDR - TRANSMIT REGISTER
8
8-bit SHIFT REGISTER
TIMING AND CONTROL
8
SPIRxD /
P1.5 or P4.5
SPISTAT - STATUS REGISTER
8
SPIRDR - RECEIVE REGISTER
8
SPITxD / P1.6 or P4.6
PERIPH_CLK
(fOSC)
CLOCK
DIVIDE
÷1
÷4
÷8
÷16
÷32
÷64
÷128
CLOCK
GENERATE
SPISEL / P1.7 or P4.7
SPICLK / P1.4 or P4.4
8
SPICLKD - DIVIDE SELECT
AI10486
24.5
SPI configuration
The SPI interface is reset by the MCU reset, and firmware needs to initialize the SFRs
SPICON0, SPICON1, and SPICLKD to define several operation parameters.
The SPO Bit in SPICON0 determines the clock polarity. When SPO is set to '0,' a data bit is
transmitted on SPITxD from one rising edge of SPICLK to the next and is guaranteed to be
valid during the falling edge of SPICLK. When SPO is set to '1,' a data bit is transmitted on
SPITxD from one falling edge of SPICLK to the next and is guaranteed to be valid during the
rising edge of SPICLK. The uPSD34xx will sample received data on the appropriate edge of
SPICLK as determined by SPO. The effect of the SPO Bit can be seen in Figure 46 and
Figure 47 on page 137.
The FLSB Bit in SPICON0 determines the bit order while transmitting and receiving the 8-bit
data. When FLSB is '0,' the 8-bit data is transferred in order from MSB (first) to LSB (last).
When FLSB Bit is set to '1,' the data is transferred in order from LSB (first) to MSB (last).
The clock signal generated on SPICLK is derived from the internal PERIPH_CLK signal.
PERIPH_CLK always operates at the frequency, f_OSC, and runs constantly except when
stopped in MCU Power Down mode. SPICLK is a result of dividing PERIPH_CLK by a sum
of different divisors selected by the value contained in the SPICLKD register. The default
value in SPICLKD after a reset divides PERIPH_CLK by a factor of 4. The bits in SPICLKD
can be set to provide resulting divisor values in of sums of multiples of 4, such as 4, 8, 12,
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