UPSD3422_06 Datasheet, PDF (279/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
Figure 107. Peripheral I/O WRITE timing
ALE
DC and AC parameters
A/D BUS
ADDRESS
DATA OUT
tWLQV (PA)
tWHQZ (PA)
WR
tDVQV (PA)
PORT A
DATA OUT
AI06611
Table 176. Port A peripheral data mode WRITE timing (5V PSD module)
Symbol
Parameter
Conditions
Min
Max Unit
t_WLQV–PA WR to Data Propagation Delay
t_DVQV–PA Data to Port A Data Propagation Delay
t_WHQZ–PA WR Invalid to Port A Tri-state
(Note 1)
25
ns
22
ns
20
ns
Note: 1 Data stable on Port 0 pins to data on Port A.
Table 177. Port A peripheral data mode WRITE timing (3V PSD module)
Symbol
Parameter
Conditions
Min
Max Unit
t_WLQV–PA WR to Data Propagation Delay
t_DVQV–PA Data to Port A Data Propagation Delay
t_WHQZ–PA WR Invalid to Port A Tri-state
(Note 1)
42
ns
38
ns
33
ns
Note: 1 Data stable on Port 0 pins to data on Port A.
Table 178. Supervisor reset and LVD
Symbol
Parameter
Conditions
Min
Typ
Max Unit
t_{RST_LO_IN} Reset Input Duration
t_{RST_ACTV} Generated Reset Duration
f_OSC = 40MHz
1⁽¹⁾
10⁽²⁾
t_{RST_FIL}
Reset Input Spike Filter
1
V_{RST_HYS} Reset Input Hysteresis
V_CC = 3.3V
0.1
V_{RST_THRE LVD Trip Threshold}
SH
V_CC = 3.3V
2.4
2.6
µs
ms
µs
V
2.8
V
Note: 1 25µs minimum to abort a Flash memory program or erase cycle in progress.
2 As f_OSC decreases, t_{RST_ACTV} increases. Example: t_{RST_ACTV} = 50ms when f_OSC = 8MHz.
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