UPSD3422_06 Datasheet, PDF (53/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx
Interrupt system
Note:
If an interrupt flag is not cleared after servicing the interrupt, an unwanted interrupt will occur
upon exiting the ISR.
After the interrupt is serviced, the last instruction executed by the ISR is RETI. The RETI
informs the MCU that the ISR is no longer in progress and the MCU pops the top two bytes
from the stack and loads them into the PC. Execution of the interrupted program continues
where it left off.
An ISR must end with a RETI instruction, not a RET. An RET will not inform the interrupt
control system that the ISR is complete, leaving the MCU to think the ISR is still in progress,
making future interrupts impossible.
Table 16. Interrupt summary
Interrupt
Source
Polling Vecto
Priority r Addr
Flag Bit Name
(SFR.bit
position)
1 = Intr
Pending
0 = No
Interrupt
Flag Bit
Auto-
Cleared
by
Hardware?
Enable Bit Name
(SFR.bit
position)
1 = Intr Enabled
0 = Intr Disabled
Priority Bit
Name
(SFR.bit
position)
1= High Priority
0 = Low Priority
Reserved 0 (high) 0063h
External
Interrupt
INT0
1 0003h
–
IE0 (TCON.1)
–
Edge - Yes
Level - No
–
EX0 (IE.0)
–
PX0 (IP.0)
Timer 0
Overflow
External
Interrupt
INT1
Timer 1
Overflow
2 000Bh TF0 (TCON.5)
Yes
Edge - Yes
3 0013h IE1 (TCON.3
Level - No
4 001Bh TF1 (TCON.7)
Yes
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
PT0 (IP.1)
PX1 (IP.2)
PT1 (IP.3)
RI (SCON0.0)
UART0
5 0023h
No
TI (SCON0.1)
Timer 2
Overflow
TF2 (T2CON.7)
or TX2
Pin
6 002Bh
EXF2
(T2CON.6)
No
SPI
USB
I²C
TEISF, RORISF,
7 0053h TISF, RISF
Yes
(SPISTAT[3:0])
8 0033h
– ⁽¹⁾
No
9 0043h INTR (S1STA.5)
Yes
ES0 (IE.4)
ET2 (IE.5)
PS0 (IP.4)
PT2 (IP.5)
ESPI (IEA.6)
PSPI (IPA.6)
EUSB (IEA.0)
EI²C (IEA.1)
PUSB (IPA.0)
PI²C (IPA.1)
ADC
10 003Bh
AINTF
(ACON.7)
No
EADC (IEA.7) PADC (IPA.7)
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