UPSD3422_06 Datasheet, PDF (42/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

uPSD34xx instruction set summary
10 uPSD34xx instruction set summary
uPSD34xx
Tables 6 through 11 list all of the instructions supported by the uPSD34xx, including the
number of bytes and number of machine cycles required to implement each instruction. This
is the standard 8051 instruction set.
The meaning of “machine cycles” is how many 8032 MCU core machine cycles are required
to execute the instruction. The “native” duration of all machine cycles is set by the memory
wait state settings in the SFR, BUSCON, and the MCU clock divider selections in the SFR,
CCON0 (i.e. a machine cycle is typically set to 4 MCU clocks for a 5V uPSD34xx). However,
an individual machine cycle may grow in duration when either of two things happen:
1. a stall is imposed while loading the 8032 Pre-Fetch Queue (PFQ); or
2. the occurrence of a cache miss in the Branch Cache (BC) during a branch in program
execution flow.
See Section 5: 8032 MCU core performance enhancements on page 23 or more details.
But generally speaking, during typical program execution, the PFQ is not empty and the BC
has no misses, producing very good performance without extending the duration of any
machine cycles.
Table 6. Arithmetic instruction set
Mnemonic⁽¹⁾ and Use
Description
ADD
ADD
A, Rn
A, Direct
Add register to ACC
Add direct byte to ACC
ADD
ADD
ADDC
ADDC
A, @Ri
A, #data
A, Rn
A, direct
Add indirect SRAM to ACC
Add immediate data to ACC
Add register to ACC with carry
Add direct byte to ACC with carry
ADDC
ADDC
SUBB
SUBB
SUBB
A, @Ri
A, #data
A, Rn
A, direct
A, @Ri
Add indirect SRAM to ACC with carry
Add immediate data to ACC with carry
Subtract register from ACC with borrow
Subtract direct byte from ACC with borrow
Subtract indirect SRAM from ACC with borrow
SUBB
INC
INC
INC
A, #data
A
Rn
direct
Subtract immediate data from ACC with borrow
Increment A
Increment register
Increment direct byte
INC
DEC
DEC
DEC
DEC
@Ri
A
Rn
direct
@Ri
Increment indirect SRAM
Decrement ACC
Decrement register
Decrement direct byte
Decrement indirect SRAM
Length/Cycles
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
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