UPSD3422_06 Datasheet, PDF(239/293 Page) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

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UPSD3422_06 Datasheet, PDF (239/293 Pages) STMicroelectronics – Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

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uPSD34xx

PSD module

if they are used for 6-pin JTAG. See Section 28.6.1: JTAG ISP and JTAG debug on

page 251 for details.

â PC2 can be used as a voltage input (from battery or other DC source) to backup

the contents of SRAM when VDD is lost. This function is specified in PSDsoft

Express as Section 28.5.62: SRAM standby mode (battery backup) on page 250.

â PC3 can be used as an output to indicate when a Flash memory program or erase

operation has completed. This is specified in PSDsoft Express as Section 28.5.12:

Ready/Busy (PC3) on page 208.

â PC4 can be used as an output to indicate when the SRAM has switched to backup

voltage (when VDD is less than the battery input voltage on PC2). This is specified

in PSDsoft Express as âStandby-On Indicatorâ (see Section 28.5.62: SRAM

standby mode (battery backup) on page 250).

The remaining four pins (TDI, TDO, TCK, TMS) on Port C are dedicated to the JTAG

function and cannot be used for any other function. See Section 28.6.1: JTAG ISP and JTAG

debug on page 251.

Port C also supports the Open Drain output drive type options on pins PC2, PC3, PC4, and

PC7 using the csiop Drive Select registers.

Figure 87. Port C structure

FROM AND-

OR ARRAY

FROM PLD

INPUT BUS

PT OUTPUT ENABLE, .OE (JTAG STATE MACHINE

AUTOMATICALLY CONTROLS OE FOR JTAG SIGNALS)

PSD MODULE RESET

Q DIRECTION

CSIOP

REGIS-

8032 TERS

DATA

Q

DRIVE

BITS D

DRIVE TYPE SELECT(2)

I/O PORT C

LOGIC

VDD/VBAT(1)

PULL-UP

ONLY ON

50k JTAG TDI,

TMS, TCK

SIGNALS

8032

WR

(MCUI/O)

DATA OUT

Q

CLR RESET

8032

DATA

BIT

1 DIRECTION

P 2 DRIVE SELECT

D DATA OUT

B 3 (MCUI/O)

M 4 ENABLE OUT

U

X 5 DATA IN (MCUI/O)

PSDsoft

1O

U

T

P

U

2T

3

4

M

U

5X

OUTPUT

ENABLE

PIN

OUTPUT

VDD

VDD/VBAT(1)

TYPICAL

PIN,

PORT C

PIN

CMOS INPUT

BUFFER

8032 RD

ONE of 6

CSIOP

REGISTERS

FROM OMC

ALLOCATOR

FROM OMC OUTPUT (MCELLBCx)

FROM SRAM

BACK-UP CIRCUIT

FROM FLASH MEMORIES

TO/FROM JTAG

STATE MACHINE

STANDBY ON(2)

RDY/BSY(2)

TDO, TSTAT(2), TERR(2)

TDI, TMS, TCK

NO

HYSTERESIS

TO IMCs

IMCC2, IMCC3,

IMCC4, IMCC7

TO SRAM

BATTERY

BACK-UP

CIRCUIT(2)

AI09181

Note: 1 Pull-up switches to VBAT when SRAM goes to battery back-up mode.

2 Optional function on a specific Port C pin.

239/293

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